公开(公告)号：US10530562B2

公开(公告)日：2020-01-07

申请号：US15493429

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Richard Andrew Paterson ,  Simon Crossley ,  Ramnath Bommu Subbiah Swamy ,  Steven Douglas Krueger ,  Anitha Kona

IPC: G06F1/12 ,  H04L12/26 ,  H04L7/00

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

公开(公告)号：US11803506B2

公开(公告)日：2023-10-31

申请号：US17512758

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Anitha Kona ,  Jacob Joseph ,  Arthur Brian Laughton ,  Nandakishore Sastry

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

公开(公告)号：US10853271B2

公开(公告)日：2020-12-01

申请号：US16053899

申请日：2018-08-03

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Jamshed Jalal ,  Andrea Pellegrini ,  Anitha Kona

IPC: G06F12/14 ,  G06F12/1081 ,  G06F13/42

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

公开(公告)号：US20200257647A1

公开(公告)日：2020-08-13

申请号：US16271015

申请日：2019-02-08

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Anitha Kona ,  Mark David Werkheiser

IPC: G06F13/42 ,  G06F13/20

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

公开(公告)号：US10725958B1

公开(公告)日：2020-07-28

申请号：US16271015

申请日：2019-02-08

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Anitha Kona ,  Mark David Werkheiser

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/20

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

公开(公告)号：US12242399B2

公开(公告)日：2025-03-04

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob Joseph ,  Tessil Thomas ,  Arthur Brian Laughton ,  Anitha Kona ,  Jamshed Jalal

IPC: G06F13/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/1045 ,  G06F13/16

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

公开(公告)号：US10606679B2

公开(公告)日：2020-03-31

申请号：US15830380

申请日：2017-12-04

Applicant: Arm Limited

Inventor： Anitha Kona ,  Michael John Williams ,  John Michael Horley ,  Alasdair Grant

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/42 ,  G06F13/24

Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

公开(公告)号：US11537543B2

公开(公告)日：2022-12-27

申请号：US17189781

申请日：2021-03-02

Applicant: Arm Limited

Inventor： Ashok Kumar Tummala ,  Jamshed Jalal ,  Antony John Harris ,  Jeffrey Carl Defilippi ,  Anitha Kona ,  Bruce James Mathewson

IPC: G06F13/38 ,  G06F13/40

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path. For a selected layer of the multiple layers, the protocol conversion circuitry provides, within the gateway component, upper selected layer circuitry to implement a first portion of functionality of the selected layer, where the first portion comprises at least protocol dependent functionality of the selected layer. It also provides, within the controller, lower selected layer circuitry to implement a remaining portion of the functionality of the selected layer, the remaining portion comprising only protocol independent functionality of the selected layer.

公开(公告)号：US11194693B2

公开(公告)日：2021-12-07

申请号：US15711028

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Anitha Kona ,  Michael John Williams ,  John Michael Horley ,  Alasdair Grant

IPC: G06F11/34

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.