公开(公告)号：US11181957B1

公开(公告)日：2021-11-23

申请号：US17102963

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Ramamoorthy Guru Prasadh ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  David Joseph Hawkins ,  Saira Samar Malik

IPC: G06F1/24 ,  H03K19/20 ,  G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K5/00

Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.

公开(公告)号：US10761561B2

公开(公告)日：2020-09-01

申请号：US15989228

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Saira Samar Malik ,  David Joseph Hawkins ,  Andrew David Tune ,  Guanghui Geng ,  Julian Jose Hilgemberg Pontes

IPC: G06F1/12 ,  G06F30/39

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.