公开(公告)号：US11853220B2

公开(公告)日：2023-12-26

申请号：US17501272

申请日：2021-10-14

Applicant: Arm Limited

Inventor： Natalya Bondarenko ,  Stefano Ghiggini ,  Damien Matthieu Valentin Cathrine ,  Ugo Castorina

IPC: G06F12/0862 ,  G06F12/0891 ,  G06F13/16 ,  G06F12/02 ,  G06F18/214

CPC classification number: G06F12/0862 ,  G06F12/0238 ,  G06F12/0891 ,  G06F13/1621 ,  G06F13/1668 ,  G06F18/214

Abstract: An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.

公开(公告)号：US12277063B1

公开(公告)日：2025-04-15

申请号：US18538160

申请日：2023-12-13

Applicant: Arm Limited

Inventor： Ugo Castorina ,  Damien Matthieu Valentin Cathrine ,  Marco Coletta ,  Diogo Augusto Pereira Marques

IPC: G06F12/0862

Abstract: An apparatus for improving the tracking of streams of memory accesses for training a stride prefetcher is provided, comprising a training data structure storing entries for training a stride prefetcher, a given entry specifying: a stride offset, a target address, a program counter address, and a bypass indicator indicating whether a program counter match condition is to be bypassed for the given entry; and training control circuitry to determine whether to update the stride offset for the given entry of the training data structure to specify a current stride between a target address of a current memory access and the target address for the last memory access of the tracked stream, in which the determination by the training control circuitry is controlled to be either dependent on a determination of whether the program counter match condition is satisfied or independent of whether the program counter match condition is satisfied, based on the bypass indicator.

公开(公告)号：US12013785B2

公开(公告)日：2024-06-18

申请号：US17988892

申请日：2022-11-17

Applicant: Arm Limited

Inventor： Ugo Castorina ,  Damien Matthieu Valentin Cathrine ,  Marco Coletta ,  Igor Burovenko

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F12/0238

Abstract: There is provided an apparatus, medium and method. The apparatus comprises candidate offset storage circuitry to store a list comprising a plurality of candidate offset values having a default order, and prefetch circuitry to generate prefetch addresses by modifying a base address using a current offset, and to issue prefetch requests to cause information beginning at a corresponding prefetch address to be prefetched into the storage structure in anticipation of a demand request for that information. The apparatus further comprises prefetch training circuitry to select a new offset from the list of candidate offset values through comparison of the plurality of candidate offset values against data indicative of recent requests. The prefetch training circuitry is configured to identify a subset of the candidate offset values based on the current offset and to dynamically modify the default order to increase priority of the subset.

公开(公告)号：US11847056B1

公开(公告)日：2023-12-19

申请号：US17824199

申请日：2022-05-25

Applicant: Arm Limited

Inventor： Damien Matthieu Valentin Cathrine ,  Ugo Castorina ,  Luca Nassi

IPC: G06F12/08 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: An apparatus comprises prefetch circuitry, and a cache having a plurality of entries to store data for access by processing circuitry and blocks of metadata for reference by the prefetch circuitry. The prefetch circuitry can detect one or more access sequences in dependence on training inputs derived from demand accesses processed by the cache in response to memory access operations performed by the processing circuitry. On detecting a given access sequence, this causes an associated given block of metadata providing information indicative of the given access sequence to be stored in a selected entry of the cache. Eviction control circuitry, responsive to a victimisation event, performs an operation to select a victim entry in the cache, the victim entry being selected from one or more candidate victim entries. Each entry has an associated age indication value used to determine whether that entry is allowed to be a candidate victim entry, and the eviction control circuitry is arranged to perform a dynamic ageing operation to determine an ageing control value used to control updating of the associated age indication value for any entry storing a block of metadata. The dynamic ageing operation is arranged to determine the ageing control value in dependence on at least a training rate indication for the prefetch circuitry, where the training rate indication is indicative of a number of training inputs per memory access operation performed by the processing circuitry.

公开(公告)号：US11675702B1

公开(公告)日：2023-06-13

申请号：US17673301

申请日：2022-02-16

Applicant: Arm Limited

Inventor： Ugo Castorina ,  Damien Matthieu Valentin Cathrine

IPC: G06F12/0862 ,  G06F12/0871 ,  G06F12/121 ,  G06F9/32 ,  G06F9/30 ,  G06F12/02 ,  G06F18/214

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/321 ,  G06F12/0238 ,  G06F12/0871 ,  G06F12/121 ,  G06F18/214

Abstract: Prefetch circuitry generates prefetch requests to prefetch information to a cache, based on prediction information trained using a training table comprising training entries. A given training entry associates a program counter indication associated with a trigger training memory access, a region indication indicative of a memory address region comprising a target address specified by the trigger training memory access, corresponding prediction information trained based on subsequent training memory access requests specifying target addresses in the same region as the target address of the trigger training memory access, and first and second replacement policy information. The first replacement policy information is used for replacement of an entry with another entry for the same program counter indication but different region. The second replacement policy information is used for replacement of an entry with another entry for a different program counter indication. This helps to increase prediction performance and reduce power consumption.