公开(公告)号：US20210383050A1

公开(公告)日：2021-12-09

申请号：US16893378

申请日：2020-06-04

Applicant: Arm Limited

Inventor： Yulin Shi ,  Vincent Philippe Schuppe ,  Ettore Amirante

IPC: G06F30/398 ,  G06F30/3953

Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.

公开(公告)号：US20170062043A1

公开(公告)日：2017-03-02

申请号：US15011042

申请日：2016-01-29

Applicant: ARM Limited

Inventor： Vincent Philippe Schuppe ,  Sushil Kumar ,  Daksheshkumar Maganbhai Malaviya ,  Hemant Hemraj Parate

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/062 ,  G11C7/08 ,  G11C7/106 ,  G11C7/14

Abstract: Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to receive complimentary data signals from complimentary bitlines and provide first and second sensed data signals based on received complimentary data signals. The second sensed data signal may be a compliment of the first sensed data signal. The device may include a balance coupler configured to receive the second sensed data signal from the sense amplifier and provide a modified second sensed data signal having capacitance similar to the first sensed data signal. The device may include a latch configured to receive the first sensed data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide a latched data signal based on the first and modified second sensed data signals.

Abstract translation: 本文描述的各种实现涉及用于动态电容平衡的装置。 该器件可以包括读出放大器，其被配置为从互补位线接收补充数据信号，并且基于接收的互补数据信号提供第一和第二感测数据信号。 第二感测数据信号可以是第一感测数据信号的补充。 该装置可以包括配置成从感测放大器接收第二检测数据信号并提供具有类似于第一感测数据信号的电容的经修改的第二检测数据信号的平衡耦合器。 该装置可以包括锁存器，其被配置为从读出放大器接收第一感测数据信号，从平衡耦合器接收经修改的第二感测数据信号，并且基于第一和修改的第二感测数据信号提供锁存数据信号。

公开(公告)号：US20200019669A1

公开(公告)日：2020-01-16

申请号：US16033158

申请日：2018-07-11

Applicant: Arm Limited

Inventor： Vincent Philippe Schuppe ,  Syam Kumar Lalitha Gopalakrishnan Nair ,  Hongwei Zhu ,  Neeraj Dogra ,  Mouli Rajaram Chollangi ,  Arjun R. Prasad

IPC: G06F17/50 ,  G11C11/412 ,  H01L27/11 ,  H01L27/02

Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.

公开(公告)号：US10403643B2

公开(公告)日：2019-09-03

申请号：US15587087

申请日：2017-05-04

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Vincent Philippe Schuppe

IPC: H01L27/118 ,  H01L27/02 ,  G06F17/50

Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.

公开(公告)号：US20180323215A1

公开(公告)日：2018-11-08

申请号：US15587087

申请日：2017-05-04

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Vincent Philippe Schuppe

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  H01L27/0207 ,  H01L2027/11866 ,  H01L2027/11881

Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.

公开(公告)号：US09570157B1

公开(公告)日：2017-02-14

申请号：US15011042

申请日：2016-01-29

Applicant: ARM Limited

Inventor： Vincent Philippe Schuppe ,  Sushil Kumar ,  Daksheshkumar Maganbhai Malaviya ,  Hemant Hemraj Parate

IPC: G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/062 ,  G11C7/08 ,  G11C7/106 ,  G11C7/14

Abstract: Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to receive complimentary data signals from complimentary bitlines and provide first and second sensed data signals based on received complimentary data signals. The second sensed data signal may be a compliment of the first sensed data signal. The device may include a balance coupler configured to receive the second sensed data signal from the sense amplifier and provide a modified second sensed data signal having capacitance similar to the first sensed data signal. The device may include a latch configured to receive the first sensed data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide a latched data signal based on the first and modified second sensed data signals.

Abstract translation: 本文描述的各种实现涉及用于动态电容平衡的装置。 该器件可以包括读出放大器，其被配置为从互补位线接收补充数据信号，并且基于接收的互补数据信号提供第一和第二感测数据信号。 第二感测数据信号可以是第一感测数据信号的补充。 该装置可以包括配置成从感测放大器接收第二检测数据信号并提供具有类似于第一感测数据信号的电容的经修改的第二检测数据信号的平衡耦合器。 该装置可以包括锁存器，其被配置为从读出放大器接收第一感测数据信号，从平衡耦合器接收经修改的第二感测数据信号，并且基于第一和修改的第二感测数据信号提供锁存数据信号。

公开(公告)号：US11475200B2

公开(公告)日：2022-10-18

申请号：US16893378

申请日：2020-06-04

Applicant: Arm Limited

Inventor： Yulin Shi ,  Vincent Philippe Schuppe ,  Ettore Amirante

IPC: G06F30/398 ,  G06F30/3953

Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.

公开(公告)号：US10579775B2

公开(公告)日：2020-03-03

申请号：US16033158

申请日：2018-07-11

Applicant: Arm Limited

Inventor： Vincent Philippe Schuppe ,  Syam Kumar Lalitha Gopalakrishnan Nair ,  Hongwei Zhu ,  Neeraj Dogra ,  Mouli Rajaram Chollangi ,  Arjun R. Prasad

IPC: G11C13/00 ,  G11C29/08 ,  G06F17/50 ,  H01L27/02 ,  G11C11/412 ,  H01L27/11

Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.