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公开(公告)号：US20050257031A1
公开(公告)日：2005-11-17
申请号：US11187068
申请日：2005-07-22
IPC分类号： G06F9/00 , G06F15/78 , H01L21/82 , H03K19/173
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。
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公开(公告)号：US07886130B2
公开(公告)日：2011-02-08
申请号：US12345409
申请日：2008-12-29
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。
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公开(公告)号：US20090106531A1
公开(公告)日：2009-04-23
申请号：US12345409
申请日：2008-12-29
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。
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公开(公告)号：US07069419B2
公开(公告)日：2006-06-27
申请号：US10821533
申请日：2004-04-08
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
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公开(公告)号：US06751723B1
公开(公告)日：2004-06-15
申请号：US09654237
申请日：2000-09-02
IPC分类号： G06F1580
CPC分类号： G06F15/7842 , G06F15/7867
摘要： An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。
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公开(公告)号：US07516303B2
公开(公告)日：2009-04-07
申请号：US11187068
申请日：2005-07-22
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.
摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。
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7.发明申请METHOD AND SYSTEM FOR ACCELERATING TRANSMISSION OF DATA BETWEEN NETWORK DEVICES 有权用于加速网络设备之间数据传输的方法和系统公开(公告)号：US20080225842A1
公开(公告)日：2008-09-18
申请号：US12041489
申请日：2008-03-03
申请人： Arnold Goldfein , David Gariepy , Robert Cousins , Laurence Brevard , Sharon A. Mylroie Goldfein
发明人： Arnold Goldfein , David Gariepy , Robert Cousins , Laurence Brevard , Sharon A. Mylroie Goldfein
IPC分类号： H04L12/28
CPC分类号： H04L47/25 , H04L1/0007 , H04L1/0009 , H04L1/0034 , H04L1/1825 , H04L1/1854 , H04L47/10 , H04L47/193
摘要： A method and system for transferring data between a sender and a receiver in a packet-based network is disclosed. The method comprises establishing a data channel, establishing a feedback channel, sending data to the receiver over the data channel, sending an acknowledgment to a sender on the feedback channel at a predetermined interval, using the acknowledgment to track data sent successfully and unsuccessfully to the receiver, resending data unsuccessfully sent to the receiver, and self-tuning to optimize throughput based upon the acknowledgement and react to changing network conditions.
摘要翻译： 公开了一种在基于分组的网络中在发送方和接收方之间传送数据的方法和系统。 该方法包括建立数据信道，建立反馈信道，通过数据信道向接收者发送数据，以预定间隔向反馈信道上的发送者发送确认，使用确认来跟踪成功发送的数据并且不成功地发送给 接收机，重新发送数据未成功发送到接收机，以及自调整，以根据确认优化吞吐量并对变化的网络条件作出反应。
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8.发明授权Method and system for accelerating transmission of data between network devices 有权用于加速网络设备间数据传输的方法和系统公开(公告)号：US08310920B2
公开(公告)日：2012-11-13
申请号：US12041489
申请日：2008-03-03
申请人： Arnold Goldfein , Sharon A. Mylroie Goldfein , David Gariepy , Robert Cousins , Laurence Brevard
发明人： Arnold Goldfein , Sharon A. Mylroie Goldfein , David Gariepy , Robert Cousins , Laurence Brevard
CPC分类号： H04L47/25 , H04L1/0007 , H04L1/0009 , H04L1/0034 , H04L1/1825 , H04L1/1854 , H04L47/10 , H04L47/193
摘要： A method and system for transferring data between a sender and a receiver in a packet-based network is disclosed. The method comprises establishing a data channel, establishing a feedback channel, sending data to the receiver over the data channel, sending an acknowledgment to a sender on the feedback channel at a predetermined interval, using the acknowledgment to track data sent successfully and unsuccessfully to the receiver, resending data unsuccessfully sent to the receiver, and self-tuning to optimize throughput based upon the acknowledgment and react to changing network conditions.
摘要翻译： 公开了一种在基于分组的网络中在发送方和接收方之间传送数据的方法和系统。 该方法包括建立数据信道，建立反馈信道，通过数据信道向接收者发送数据，以预定间隔向反馈信道上的发送者发送确认，使用确认来跟踪成功发送的数据并且不成功地发送给 接收机，重新发送数据未成功发送到接收机，以及自调整，以根据确认优化吞吐量并对变化的网络条件作出反应。
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