公开(公告)号：US20080048717A1

公开(公告)日：2008-02-28

申请号：US11931772

申请日：2007-10-31

申请人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kolkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William Plants

发明人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kolkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

摘要翻译： 一种可编程片上系统集成电路装置，包括可编程逻辑块，非易失性存储块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块。 可编程互连架构包括可编程元件和互连导体。 可编程元件的一部分耦合到可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得 可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输入和输出可以可编程地彼此耦合。

公开(公告)号：US20070189062A1

公开(公告)日：2007-08-16

申请号：US11740458

申请日：2007-04-26

申请人： William Plants

发明人： William Plants

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C14/00 ,  G11C11/412 ,  G11C14/0063 ,  H03K19/1776

摘要： First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

摘要翻译： 第一和第二互补静态随机存取存储器单元位线通过由字线控制的第一和第二存取晶体管耦合到第一和第二位节点。 第一反相器具有耦合到第一位节点的输入和耦合到第二位节点的输出。 第二反相器具有耦合到第二位节点的输入和通过第一晶体管开关耦合到第一位节点的输出。 晶体管开关耦合在非易失性存储单元的输出和第一位节点之间。 耦合到晶体管开关的栅极的控制电路。 选择非易失性存储单元的驱动电平以使第二反相器的输出过压，或者第二反相器与第一位节点去耦，而非易失性存储单元的输出耦合到第一位节点。

公开(公告)号：US20060087341A1

公开(公告)日：2006-04-27

申请号：US11295889

申请日：2005-12-06

申请人： William Plants ,  Arunangshu Kundu

发明人： William Plants ,  Arunangshu Kundu

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17744

摘要： A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.

公开(公告)号：US20050257031A1

公开(公告)日：2005-11-17

申请号：US11187068

申请日：2005-07-22

申请人： Arunangshu Kundu ,  Arnold Goldfein ,  William Plants ,  David Hightower

发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William Plants ,  David Hightower

IPC分类号： G06F9/00 ,  G06F15/78 ,  H01L21/82 ,  H03K19/173

CPC分类号： G06F15/7842 ,  G06F15/7867

摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

公开(公告)号：US20050146354A1

公开(公告)日：2005-07-07

申请号：US11074922

申请日：2005-03-07

申请人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William Plants

发明人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William Plants

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

摘要翻译： 具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。 逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。 第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构 组件。

公开(公告)号：US20080007288A1

公开(公告)日：2008-01-10

申请号：US11859497

申请日：2007-09-21

申请人： William Plants

发明人： William Plants

IPC分类号： H01L21/82

CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

公开(公告)号：US20070103966A1

公开(公告)日：2007-05-10

申请号：US11617559

申请日：2006-12-28

申请人： William Plants

发明人： William Plants

IPC分类号： G11C11/00

CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

公开(公告)号：US20050081177A1

公开(公告)日：2005-04-14

申请号：US10916214

申请日：2004-08-10

申请人： Samuel Beal ,  Sinan Kaptonoglu ,  Jung-Cheun Lien ,  William Shu ,  King Chan ,  William Plants

发明人： Samuel Beal ,  Sinan Kaptonoglu ,  Jung-Cheun Lien ,  William Shu ,  King Chan ,  William Plants

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC分类号： H03K19/17768 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-progamable gate array and the integrated circuit I/O.

摘要翻译： 增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。 电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

公开(公告)号：US5576560A

公开(公告)日：1996-11-19

申请号：US267036

申请日：1994-06-27

申请人： Thomas J. Runaldue ,  William Plants

发明人： Thomas J. Runaldue ,  William Plants

IPC分类号： G09G5/00 ,  G06T1/20 ,  G06T1/60 ,  G09G5/06 ,  G11C7/10 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/10

CPC分类号： H01L27/1104 ,  G09G5/06 ,  G11C7/1075 ,  Y10S257/903

摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory.Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.A layout configuration of each memory cell and of the memory cell array allows same-channel-type transistors from a plurality of memory cells to be formed in a single, large well, and allows adjacent memory cells to share contacts. This reduces the integrated circuit's size, improves its speed, and increases manufacturing yields.

摘要翻译： 一种用于显示系统的颜色查找表的集成电路存储器。 存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。 每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。 视频端口包括隔离的感测端子和两个晶体管。 第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。 第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。 每个存储单元和存储单元阵列的布局配置允许在单个大的阱中形成来自多个存储单元的相同通道型晶体管，并允许相邻的存储单元共享触点。 这降低了集成电路的尺寸，提高了其速度，并提高了制造成品率。

公开(公告)号：US5325338A

公开(公告)日：1994-06-28

申请号：US754910

申请日：1991-09-04

申请人： Thomas J. Runaldue ,  William Plants

发明人： Thomas J. Runaldue ,  William Plants

IPC分类号： G09G5/00 ,  G06T1/20 ,  G06T1/60 ,  G09G5/06 ,  G11C7/10 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00 ,  G09G1/28

CPC分类号： H01L27/1104 ,  G09G5/06 ,  G11C7/1075 ,  Y10S257/903

摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory. Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.

摘要翻译： 一种用于显示系统的颜色查找表的集成电路存储器。 存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。 每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。 视频端口包括隔离的感测端子和两个晶体管。 第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。 第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。