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    Analytical constraint generation for cut-based global placement
    3.
    发明授权
    Analytical constraint generation for cut-based global placement 有权

    公开(公告)号：US06671867B2

    公开(公告)日：2003-12-30

    申请号：US10121877

    申请日：2002-04-11

    申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Paul G. Villarrubia

    发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Paul G. Villarrubia

    IPC分类号： G06F945

    CPC分类号： G06F17/5072

    摘要： A method of designing the layout of an integrated circuit (IC) by deriving an analytical constraint for a cut-based placement partitioner using analytical optimization, and placing cells on the IC with the cut-based placement partitioner using the analytical constraint. Quadratic optimization may be used to determine a desired ratio of a cell area of a given partition to a total cell area (the balance parameter), and placing may be performed using multilevel bisection partitioning constrained by the balance parameter. This implementation may include a determination of an aspect ratio for an entire partitioning region of the integrated circuit, and a “center-of-mass” coordinate of the cells based on the quadratic optimization, which are then used to define a placement rectangle having the same aspect ratio, and centered on the center-of-mass coordinate. This placement rectangle is used to derive the balance parameter. The placement rectangle has a total area equal to a total moveable cell area, and the balance parameter is computed by calculating the ratio of a left portion of the placement rectangle which lies in the left partition to the total area of the placement rectangle. The multilevel partitioner then places a proportionate number of the cells in the left partition based on the balance parameter.

    Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors
    5.
    发明授权
    Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors 有权
    通过调制扩展力矢量来减少分析放置技术的长度的方法

    公开(公告)号：US07882475B2

    公开(公告)日：2011-02-01

    申请号：US12181447

    申请日：2008-07-29

    申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5072

    摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.

    摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

    Constrained detailed placement
    6.
    发明授权
    Constrained detailed placement 有权
    约束详细的布置

    公开(公告)号：US07467369B2

    公开(公告)日：2008-12-16

    申请号：US11554235

    申请日：2006-10-30

    申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

    发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5072

    摘要： The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. the process computes a weighted total wire length incremented value for the transformed data set. Further, the process continues by evaluating arrival time constraints, electrical constraints, and user configurable move limits for violations, and restoring the move cells to the original placement if a violation is found.

    摘要翻译： 说明性实施例提供了一种计算机实现的方法，其执行减小总线长度的小区变换，而不降低设备定时或违反电气约束。 该过程计算数据集的延迟约束系数。 该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。 该过程计算用于变换数据集合的加权总线长度递增值。 此外，该过程通过评估抵达时间约束，电气约束和用户可配置的违规移动限制，以及如果发现违规，则将移动单元恢复到原始位置继续。

    METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS
    7.
    发明申请
    METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 有权
    通过扩展力矢量调制降低分析放置技术的线性的方法

    公开(公告)号：US20080282213A1

    公开(公告)日：2008-11-13

    申请号：US12181447

    申请日：2008-07-29

    申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.

    摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

    CONSTRAINED DETAILED PLACEMENT
    8.
    发明申请
    CONSTRAINED DETAILED PLACEMENT 有权
    约束的详细布置

    公开(公告)号：US20080127017A1

    公开(公告)日：2008-05-29

    申请号：US11554235

    申请日：2006-10-30

    申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

    发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A computer implemented method and a computer program product which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set. The process performs a detailed placement transform by moving a subset of cells, making the placement legal, computing a half perimeter wire length change for each output net that is a member of the subset of nets, and computing a Manhattan distance change for each source-sink gate pair within the move cells. The process computes a weighted total wire length incremented value for the transformed data set, if the move will not improve placement, the move transform is not allowed. Further, the process continues by evaluating arrival time constraints, electrical constraints and user configurable move limits for violations, restoring the move cells to the original placement if a violation is found.

    摘要翻译： 一种计算机实现的方法和一种计算机程序产品，其执行减少总线长度的小区变换，而不会降低设备定时或违反电气限制。 该过程计算数据集的延迟约束系数。 该过程通过移动单元的子集来执行详细的放置变换，使得放置合法，计算作为网络子集成员的每个输出网的半周长线长度变化，以及计算每个源 - 移动细胞内的宿闸对。 该过程计算变换数据集的加权总线长度递增值，如果移动不会改善放置，则不允许移动变换。 此外，该过程通过评估到达时间约束，电气约束和用户可配置的违规移动限制来继续，如果发现违规，则将移动单元恢复到原始位置。

    DETAILED ROUTABILITY BY CELL PLACEMENT
    9.
    发明申请
    DETAILED ROUTABILITY BY CELL PLACEMENT 有权
    细节放置的详细的不可靠性

    公开(公告)号：US20110302545A1

    公开(公告)日：2011-12-08

    申请号：US12796501

    申请日：2010-06-08

    申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

    摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

    Clock aware placement
    10.
    发明授权
    Clock aware placement 失效
    时钟感知放置

    公开(公告)号：US07624366B2

    公开(公告)日：2009-11-24

    申请号：US11554637

    申请日：2006-10-31

    申请人： Charles J. Alpert ,  David J. Hathaway ,  William R. Migatz ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

    发明人： Charles J. Alpert ,  David J. Hathaway ,  William R. Migatz ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

    摘要翻译： 锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。 锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。 锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。 可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。 最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。