公开(公告)号：US20180046582A1

公开(公告)日：2018-02-15

申请号：US15294413

申请日：2016-10-14

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sylvain Garnier ,  Ian Fullerton ,  Xavier Leprevost

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

公开(公告)号：US09146887B2

公开(公告)日：2015-09-29

申请号：US13692531

申请日：2012-12-03

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Sylvain Garnier ,  Thierry Delalande ,  Romain Oddoart

IPC: G06F3/00 ,  G09G3/36 ,  G06F13/32

CPC classification number: G06F13/32 ,  G06F13/4234 ,  G09G3/36

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract translation: 一种设备包括中央处理单元（CPU），被配置为用于控制数字显示器的显示控制器和被配置为存储对应于数字显示器的数据的存储器。 该设备包括直接存储器访问（DMA）控制器，其被配置为在没有CPU干预的情况下将数据从存储器自动地直接传送到显示器控制器。

公开(公告)号：US10204057B2

公开(公告)日：2019-02-12

申请号：US15294413

申请日：2016-10-14

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sylvain Garnier ,  Ian Fullerton ,  Xavier Leprevost

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/02 ,  G06F3/06

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

公开(公告)号：US09423843B2

公开(公告)日：2016-08-23

申请号：US13624651

申请日：2012-09-21

Applicant: Atmel Corporation

Inventor： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

IPC: G06F1/24 ,  G06F11/267

CPC classification number: G06F1/24 ,  G06F11/267

Abstract: Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.

Abstract translation: 描述了处理器复位保持控制的系统和技术。 所描述的系统包括控制器，用于基于外部复位信号和外部调试信号检测保持请求，并且基于对保持信号的检测产生保持信号，其中保持信号在外部复位信号中断之后继续 ; 响应于外部复位信号的系统组件; 响应于所述保持信号的处理器，其中所述保持信号使所述处理器进入复位状态，并且在所述外部复位信号已经中断之后保持所述复位状态; 以及被配置为在处理器处于复位状态时允许对系统组件的外部访问的系统管理器。 控制器可以被配置为响应于明确的请求中断保持信号。