公开(公告)号：US20140281156A1

公开(公告)日：2014-09-18

申请号：US13941671

申请日：2013-07-15

Applicant: ATMEL CORPORATION

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US10073661B2

公开(公告)日：2018-09-11

申请号：US15385810

申请日：2016-12-20

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Ian Fullerton ,  Joseph Martinez ,  Martin Olsson

IPC: G11C8/00 ,  G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/062 ,  G06F3/0655 ,  G06F12/0246 ,  G06F21/6218 ,  G06F2212/1052 ,  G06F2212/72 ,  G06F2212/7201

Abstract: The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.

公开(公告)号：US09710169B2

公开(公告)日：2017-07-18

申请号：US15223227

申请日：2016-07-29

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

公开(公告)号：US09772970B2

公开(公告)日：2017-09-26

申请号：US14014128

申请日：2013-08-29

Applicant: Atmel Corporation

Inventor： Yong Luo ,  Ian Fullerton ,  Benjamin Francis Froemming ,  Morten Werner Lund

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F13/4291 ,  G06F13/4295

Abstract: Systems and methods for multi-protocol serial communication interfaces are described. One example system includes an interface module including a buffer for storing a protocol selection. The system includes a protocol module coupled to the interface module and configured for providing one or more serial communication protocols. Based on the protocol selection, one of the serial communication protocols is selected. The system also includes a serial engine module coupled to the interface module and the protocol module. The serial engine module is configured for transmitting and receiving data or commands based on the selected serial communication protocol.

公开(公告)号：US20160335000A1

公开(公告)日：2016-11-17

申请号：US15223227

申请日：2016-07-29

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US20140320189A1

公开(公告)日：2014-10-30

申请号：US13873013

申请日：2013-04-29

Applicant: ATMEL CORPORATION

Inventor： Morten Lund ,  Ian Fullerton

IPC: H03K5/13

CPC classification number: H03K5/131 ,  G06F13/4291

Abstract: A circuit is disclosed that provides a programmable hold time for a bus signal without running a system clock and without a frequency requirement between the system clock and a bus clock.

Abstract translation: 公开了一种电路，其提供总线信号的可编程保持时间，而不运行系统时钟，并且在系统时钟和总线时钟之间没有频率要求。

公开(公告)号：US20180046582A1

公开(公告)日：2018-02-15

申请号：US15294413

申请日：2016-10-14

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sylvain Garnier ,  Ian Fullerton ,  Xavier Leprevost

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

公开(公告)号：US08878569B1

公开(公告)日：2014-11-04

申请号：US13868930

申请日：2013-04-23

Applicant: Atmel Corporation

Inventor： Ian Fullerton

IPC: H03K19/00

CPC classification number: H03K19/0021

Abstract: A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a START signal that can be latched, so that the START signal can be used to wake up a system or for other purposes. To detect a STOP condition, asynchronous sequential logic is set by a transition (e.g., low to high) of the first bus signal and a second bus signal (e.g., a high signal), producing a STOP signal that can be used to reset the asynchronous sequential logic and the latch.

Abstract translation: 公开了一种检测总线信号状况的检测器电路。 为了检测START条件，异步顺序逻辑检测第一总线信号转换（例如从高到低）和第二总线信号（例如，高信号）。 异步顺序逻辑的输出被组合以产生可被锁存的START信号，使得START信号可用于唤醒系统或用于其他目的。 为了检测STOP状态，通过第一总线信号的转变（例如，从低到高）和第二总线信号（例如，高信号）来设置异步顺序逻辑，产生可用于复位的停止信号 异步顺序逻辑和锁存。

公开(公告)号：US20140312929A1

公开(公告)日：2014-10-23

申请号：US13868930

申请日：2013-04-23

Applicant: ATMEL CORPORATION

Inventor： Ian Fullerton

IPC: H03K19/00

CPC classification number: H03K19/0021

Abstract: A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a START signal that can be latched, so that the START signal can be used to wake up a system or for other purposes. To detect a STOP condition, asynchronous sequential logic is set by a transition (e.g., low to high) of the first bus signal and a second bus signal (e.g., a high signal), producing a STOP signal that can be used to reset the asynchronous sequential logic and the latch.

Abstract translation: 公开了一种检测总线信号状况的检测器电路。 为了检测START条件，异步顺序逻辑检测第一总线信号转换（例如从高到低）和第二总线信号（例如，高信号）。 异步顺序逻辑的输出被组合以产生可被锁存的START信号，使得START信号可用于唤醒系统或用于其他目的。 为了检测STOP状态，通过第一总线信号的转变（例如，从低到高）和第二总线信号（例如，高信号）来设置异步顺序逻辑，产生可用于复位的停止信号 异步顺序逻辑和锁存。

公开(公告)号：US10204057B2

公开(公告)日：2019-02-12

申请号：US15294413

申请日：2016-10-14

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sylvain Garnier ,  Ian Fullerton ,  Xavier Leprevost

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/02 ,  G06F3/06

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.