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公开(公告)号：US5056120A
公开(公告)日：1991-10-08
申请号：US381389
申请日：1989-07-18
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H04L7/005
摘要： A phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock. The phase adjusting circuit includes a plurality of registers. Each bit of data is input into a corresponding one of the plurality of registers in a predetermined cyclic order, synchronized with a receiving clock which is extracted from the data, and outputting outputs of the registers in parallel. The outputs are each selected in a selector circuit under a control of the selector control signal in the same order as the above input to the registers. The selector control signal is generated by detecting a phase relationship between phases of the receiving clock and the system clock, and generating a selector control signal having a phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock.
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公开(公告)号：US5099477A
公开(公告)日：1992-03-24
申请号：US554361
申请日：1990-07-19
CPC分类号： H04J3/0626 , H04L7/005
摘要： A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region. The phase matching circuit includes an input buffer for taking first data with a first clock; an output buffer sending second data with a second clock; a phase detector for comparing the phases of first and second clocks and detecting a phase difference within a predetermined value; a phase control unit for directly outputting the first data to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data phase shifted to the output buffer, and for converting the first data synchronized with the first clock to the second data of the same content as the first data synchronized with the second clock in the same frequency as the first clock; an invalid data region detector for detecting an invalid region of first data; and a phase shifter controller for inhibiting phase shift control in the phase control unit when the invalid data region detector does not detect the invalid region and for allowing phase shift control in the phase control unit when the invalid data region detector detects the invalid region.
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3.发明授权Easy detection of head position of information data via reception processing unit in synchronous multiplex transmission apparatus 失效通过同步多路传输装置中的接收处理单元容易地检测信息数据的头部位置
公开(公告)号：US5020057A
公开(公告)日：1991-05-28
申请号：US444864
申请日：1989-12-04
CPC分类号： H04J3/0623
摘要： A reception processing unit receives digital data in successive data frames, each frame comprising a supervisory data field and an associated information data field and, further, a negative stuff or a positive stuff in accordance with need, and detects the head position of the information data field. An enable signal is produced only during and throughout a time interval in which the information data field appears in each successive, received data frame; a count operation of a counter is performed only during the interval of the enable signal. The head position is detected each time the counter finishes counting a number of bytes equal to the fixed length of the information data field.
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4.发明授权
公开(公告)号：US5475675A
公开(公告)日：1995-12-12
申请号：US850829
申请日：1992-03-13
CPC分类号： H04L49/552 , H04L2012/5627 , H04L2012/5674
摘要： According to the present invention, when a current system is switched to a spare system in a transmission system in an asynchronous transfer mode, empty cells transmitted in the current and spare systems are detected, and thereby a timing for switching the current system to the spare system is determined. When no phase difference is existent between the current and spare systems, an empty cell is detected in both the current and spare systems at the same time. Therefore, the current system is switched to the spare system, when an empty cell is detected in both the current and spare systems at the same time. When a shade difference is existent, if an empty cell is detected either in the current or spare systems, another empty cell is inserted in to the systems. Then, the data of the empty cell in a spare system is saved. After the empty cell in a current system passes, the current system is switched to the spare system. When a phase difference of at least one cell is existent, and if an empty cell comes earlier in current system, empty cell are kept inserted form when the empty cell is detected in the current system until an empty cell is detected in the spare system. After that, the current system is switched to the spare system. When an empty cell comes earlier in a spare system, the data of the cell in the spare system is saved from when the empty cell is detected until an empty cell is detected in the current system. After that, the current system is switched to the spare system.
摘要翻译： 根据本发明，当以异步传输模式将当前系统切换到传输系统中的备用系统时，检测在当前系统和备用系统中发送的空单元，从而将当前系统切换到备用 系统确定。 当当前系统和备用系统之间没有相位差时，同时在当前系统和备用系统中检测到一个空单元。 因此，当同时在当前系统和备用系统中检测到一个空单元时，将当前系统切换到备用系统。 当存在阴影差异时，如果在当前或备用系统中检测到空单元，则将另一个空单元插入到系统中。 然后，保存备用系统中的空单元的数据。 当前系统中的空单元通过后，当前系统将切换到备用系统。 当存在至少一个小区的相位差时，如果当前系统中的空单元较早，则当在当前系统中检测到空单元时，空单元被保持插入，直到在备用系统中检测到空单元。 之后，将当前系统切换到备用系统。 当一个空单元在较早的备用系统中时，备用系统中的单元的数据将从检测到空单元到当前系统中检测到空单元之前保存。 之后，将当前系统切换到备用系统。
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公开(公告)号：US06504824B1
公开(公告)日：2003-01-07
申请号：US09235934
申请日：1999-01-22
申请人： Jun Tanaka , Takaaki Wakisaka , Tomohiro Ishihara
发明人： Jun Tanaka , Takaaki Wakisaka , Tomohiro Ishihara
IPC分类号： H04L100
CPC分类号： H04L12/5602 , H04L12/5601 , H04L2012/5636 , H04L2012/5682 , H04Q11/0478
摘要： A re-calculator circuit obtains the MCR value of each connection stored in an MCR storage unit, and performs a calculation in such a way as to impartially distribute the available rate band of a FIFO among active connections. The re-calculator circuit stores a rate band attached to the MCR value of each active connection by this calculation, in a virtual MCR storing unit as a virtual MCR value. This rate measurement unit refers to the virtual MCR value stored in the virtual MCR storage unit, and judges whether or not the input cell rate of each active connection exceeds the virtual MCR value. This result is inputted to an input control unit. The input control unit examines the input cell rate information and congestion monitoring information inputted from a queue length monitor unit for monitoring the volume of cells buffered in the FIFO, and determines whether to discard the incoming cell or to input the cell to the FIFO.
摘要翻译： 重新计算器电路获得存储在MCR存储单元中的每个连接的MCR值，并且以这样的方式进行计算，以便在活动连接中公正地分配FIFO的可用速率带。 重计算器电路通过该计算将虚拟MCR存储单元中附加到每个活动连接的MCR值的速率带存储为虚拟MCR值。 该速率测量单元是指存储在虚拟MCR存储单元中的虚拟MCR值，并且判断每个活动连接的输入单元速率是否超过虚拟MCR值。 该结果被输入到输入控制单元。 输入控制单元检查从队列长度监视器单元输入的输入信元速率信息和拥塞监视信息，用于监视在FIFO中缓存的信元的数量，并确定是丢弃传入信元还是将信元输入FIFO。
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6.发明授权Synchronization circuit for establishing frame synchronism using pointers in a digital transmission system 失效同步电路，用于在数字传输系统中使用指针建立帧同步
公开(公告)号：US5282206A
公开(公告)日：1994-01-25
申请号：US984925
申请日：1992-12-03
CPC分类号： H04J3/0608 , H04J2203/0089
摘要： A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse signal being synchronized with the beginning of the information part.
摘要翻译： 同步电路包括与第一时钟信号同步工作的第一电路块和与频率低于第一时钟信号的频率的第二时钟信号同步工作的第二电路块。 第一电路块包括帧同步电路，用于检测包含在具有监视控制数据部分和信息部分的帧格式的输入数据中的同步模式，所述监控控制数据部分包括指示信息部分的开始的指针信息。 第一电路块包括同步单元，用于从同步模式产生用于使第二电路块的操作与第一电路块的操作同步的同步控制信号。 第一电路块包括用于从第一时钟信号产生第一帧脉冲信号的脉冲发生器。 第二电路块包括：信息部分检测单元，用于产生具有比来自第二时钟信号和同步控制信号的第一帧脉冲信号低的频率的第二帧脉冲信号，第一帧脉冲信号与开始同步 的信息部分。
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公开(公告)号：US06473432B1
公开(公告)日：2002-10-29
申请号：US09023962
申请日：1998-02-13
IPC分类号： H04L1228
CPC分类号： H04Q11/0478 , H04L2012/5672 , H04L2012/5681
摘要： The present invention relates to a buffer control apparatus and method. In a buffer control apparatus for controlling storage process for a common buffer which is commonly used for a plurality of routes and temporarily stores data received from the routes, the buffer control apparatus comprises a route discriminating section for identifying the routes of the received data; a storage section for storing at least information concerning a storing position for the received data within the common buffer for each of the routes; and a control section for performing a control operation for virtually storing, route by route, the received data into the common buffer according to a result of route identification in the route discriminating section and the information concerning the storing position in the storage section, whereby the storage control in the common buffer is performed such that the common buffer can be virtually used as discrete buffers, in order to secure minimum band for each of the routes without increasing the capacity of the buffer and complicating the readout control for the buffer.
摘要翻译： 本发明涉及一种缓冲控制装置和方法。 在用于控制通常用于多个路由的公共缓冲器的存储处理的缓冲器控制装置中，临时存储从路径接收的数据，缓冲器控制装置包括用于识别接收数据的路由的路由识别部分; 存储部分，用于至少存储关于每个路线的公共缓冲器内的接收数据的存储位置的信息; 以及控制部分，用于根据路线识别部分中的路线识别结果和与存储部分中的存储位置有关的信息进行虚拟存储，路由将接收到的数据路由到公共缓冲器中的控制操作，由此， 执行公共缓冲器中的存储控制，使得公共缓冲器可以虚拟地用作离散缓冲器，以便为每个路由保证最小带宽，而不增加缓冲器的容量并使缓冲器的读出控制变得复杂。
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