公开(公告)号：US20060012403A1

公开(公告)日：2006-01-19

申请号：US10890084

申请日：2004-07-13

申请人： Atsushi Kawasumi ,  Takaaki Nakazato

发明人： Atsushi Kawasumi ,  Takaaki Nakazato

IPC分类号： G01R19/00

CPC分类号： G11C7/08

摘要： Systems and methods for reducing or eliminating the effect of timing variations in signals generated by devices that are subject to the history effect, wherein devices are enabled using a combination of timing signals, some of which are subject to timing variations arising from the history effect, and some of which are not. In one embodiment, a sense amplifier includes a pair of serially configured transistors that couple the sense amplifier to ground. One of the transistors is switched on/off by a clock signal that is not subject to history-effect timing variations, and the other is switched on/off by a signal that is subject to such variations. The second signal has pulses that are selectively delayed so that they will (or will not) overlap with the pulses of the clock signal in a controlled manner.

摘要翻译： 用于减少或消除由经历历史效应的设备产生的信号中的定时变化的影响的系统和方法，其中使用定时信号的组合启用设备，其中一些定时信号中的一些受历史效应引起的定时变化， 其中一些不是。 在一个实施例中，读出放大器包括将感测放大器耦合到地的一对串联配置的晶体管。 其中一个晶体管由不受历史效应定时变化影响的时钟信号导通/截止，另一个由受到这种变化的信号导通/关断。 第二信号具有选择性延迟的脉冲，使得它们（或将不会）以受控的方式与时钟信号的脉冲重叠。

公开(公告)号：US06833736B2

公开(公告)日：2004-12-21

申请号：US10359805

申请日：2003-02-07

申请人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong ,  Atsushi Kawasumi

发明人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong ,  Atsushi Kawasumi

IPC分类号： H03K908

CPC分类号： H03K5/1565 ,  H03K5/05 ,  H03K5/06

摘要： A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

公开(公告)号：US20070279965A1

公开(公告)日：2007-12-06

申请号：US11444019

申请日：2006-05-31

申请人： Takaaki Nakazato ,  Atsushi Kawasumi

发明人： Takaaki Nakazato ,  Atsushi Kawasumi

IPC分类号： G11C11/00

CPC分类号： G11C11/4125 ,  G11C8/16 ,  G11C11/419

摘要： Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a transfer device controlled by a pre-read signal. In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable. By shifting the bitline voltage before the wordline is turned on, the accessed cell is relieved from the stress which would have otherwise caused cell stability problems.

摘要翻译： 公开了用于避免由静态随机存取存储器（SRAM）单元中的单元稳定性问题引起的单元数据破坏的方法和装置的实施例。 在一个实施例中，利用由预读信号控制的传送装置，在实际的读/写操作之前，将SRAM单元内的数据传送到其位线之一。 在一个实施例中，读取和写入位线是共享的，并且不需要传送装置和传送装置。 由于位线电压已经被改变为预先反映单元数据的状态，所以存储单元保持相对稳定。 通过在字线打开之前移动位线电压，所访问的单元将从应力消除，否则将导致单元稳定性问题。

公开(公告)号：US07071737B2

公开(公告)日：2006-07-04

申请号：US10890084

申请日：2004-07-13

申请人： Atsushi Kawasumi ,  Takaaki Nakazato

发明人： Atsushi Kawasumi ,  Takaaki Nakazato

IPC分类号： G11C7/00 ,  G01R19/00

CPC分类号： G11C7/08

摘要： Systems and methods for reducing or eliminating the effect of timing variations in signals generated by devices that are subject to the history effect, wherein devices are enabled using a combination of timing signals, some of which are subject to timing variations arising from the history effect, and some of which are not. In one embodiment, a sense amplifier includes a pair of serially configured transistors that couple the sense amplifier to ground. One of the transistors is switched on/off by a clock signal that is not subject to history-effect timing variations, and the other is switched on/off by a signal that is subject to such variations. The second signal has pulses that are selectively delayed so that they will (or will not) overlap with the pulses of the clock signal in a controlled manner.

公开(公告)号：US20080013388A1

公开(公告)日：2008-01-17

申请号：US11457507

申请日：2006-07-14

申请人： Toru Asano ,  Sang H. Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

发明人： Toru Asano ,  Sang H. Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/848

摘要： A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.

摘要翻译： 公开了一种包括具有冗余字线的存储器阵列的存储器系统。 存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。 存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。 移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

公开(公告)号：US20070043895A1

公开(公告)日：2007-02-22

申请号：US11204417

申请日：2005-08-16

申请人： Chad Adams ,  Toru Asano ,  Sang Dhong ,  Takaaki Nakazato ,  Joel Silberman ,  Osamu Takahashi

发明人： Chad Adams ,  Toru Asano ,  Sang Dhong ,  Takaaki Nakazato ,  Joel Silberman ,  Osamu Takahashi

IPC分类号： G06F12/06 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3275 ,  G11C8/08 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/152

摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.

摘要翻译： 提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。 通常，微处理器阵列可以分为多个子阵列。 此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。 为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。 因此，省去了未使用的亚军消耗的电力。

公开(公告)号：US07053668B2

公开(公告)日：2006-05-30

申请号：US10852863

申请日：2004-05-25

申请人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

发明人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC分类号： H03K3/012 ,  G11C7/065 ,  H03K3/356139

摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

摘要翻译： 用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。 在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少 通过位线晶体管的动作将中间节点处的电压拉低。 在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

公开(公告)号：US20050264322A1

公开(公告)日：2005-12-01

申请号：US10852868

申请日：2004-05-25

申请人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

发明人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  H03F3/45 ,  H03K3/356 ,  H03K19/0948

CPC分类号： G11C7/065 ,  G11C7/12 ,  H03F3/45183 ,  H03F2203/45318

摘要： Systems and methods for pre-charging opposing nodes in a sense amplifier to substantially the same voltage in order to reduce or eliminate malfunctions arising from differences in threshold voltages of transistors coupled to the opposing nodes. One embodiment is a method including providing a silicon-on-insulator (SOI) sense amplifier having intermediate nodes between the transistors coupling each output data line to the corresponding input bit line and pre-charging each intermediate node to a predetermined voltage while the sense amplifier is not enabled. In one embodiment, the intermediate nodes are pre-charged by coupling them to a voltage source through pre-charge paths that do not include the data line pull-down transistors. In one embodiment, the method also includes decoupling the pre-charge paths after pre-charging the intermediate nodes and then enabling the sense amplifier.

摘要翻译： 用于将读出放大器中的相对节点预充电到基本相同的电压的系统和方法，以便减少或消除由耦合到相对节点的晶体管的阈值电压的差异引起的故障。 一个实施例是一种方法，包括提供绝缘体上硅（SOI）读出放大器，该晶体管在晶体管之间具有中间节点，每个晶体管将每个输出数据线耦合到相应的输入位线，并将每个中间节点预充电到预定电压，而读出放大器 未启用 在一个实施例中，中间节点通过不包括数据线下拉晶体管的预充电路径将其耦合到电压源进行预充电。 在一个实施例中，该方法还包括在对中间节点预充电然后启用读出放大器之后去耦合预充电路径。

公开(公告)号：US06898135B2

公开(公告)日：2005-05-24

申请号：US10606587

申请日：2003-06-26

申请人： Toru Asano ,  Sang Hoo Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

发明人： Toru Asano ,  Sang Hoo Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/1051

摘要： Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.

摘要翻译： 公开了一种克服与流水线存储器电路相关的读出路径中的信号延迟问题的装置和方法。 闩锁型读出放大器（SA）用于在读出之前的一个周期中的预充电状态期间接收存储单元逻辑电平。 因此，SA可以在读取锁存时钟周期期间快速提供输出信号。 SA输出通过一个动态使能的逻辑电路被传送到一个锁存电路，用于保持接收逻辑值用于下一个时钟周期。

公开(公告)号：US07423921B2

公开(公告)日：2008-09-09

申请号：US11457507

申请日：2006-07-14

申请人： Toru Asano ,  Sang H. Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

发明人： Toru Asano ,  Sang H. Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

IPC分类号： G11C7/00

CPC分类号： G11C29/848

摘要： A memory system including a memory array with redundant wordlines. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.

摘要翻译： 包括具有冗余字线的存储器阵列的存储器系统。 存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。 存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。 移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。