公开(公告)号：US09577011B2

公开(公告)日：2017-02-21

申请号：US14720997

申请日：2015-05-26

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L27/28 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/441 ,  H01L21/467 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

公开(公告)号：US20150255516A1

公开(公告)日：2015-09-10

申请号：US14720997

申请日：2015-05-26

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L27/28 ,  H01L21/441 ,  H01L51/05 ,  H01L51/00 ,  H01L21/467 ,  H01L29/66

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

公开(公告)号：US20140087525A1

公开(公告)日：2014-03-27

申请号：US14092953

申请日：2013-11-28

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L29/66

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

公开(公告)号：US09082792B2

公开(公告)日：2015-07-14

申请号：US14092953

申请日：2013-11-28

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L27/12 ,  H01L27/28 ,  H01L29/786 ,  H01L51/00

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。