公开(公告)号：US11747688B2

公开(公告)日：2023-09-05

申请号：US17901241

申请日：2022-09-01

Applicant: AU OPTRONICS CORPORATION

Inventor： Chih-Chung Su ,  Yi-Wei Chen

IPC: G02F1/1362 ,  G02F1/1335 ,  G02F1/1333

CPC classification number: G02F1/136213 ,  G02F1/133512 ,  G02F1/133388

Abstract: The present disclosure provides an electronic device. The electronic device includes a first substrate, a second substrate opposite to the first substrate, a buffer layer disposed on the second substrate, a protection layer, an active array, a pixel array, and an alignment film. The first substrate includes a transmitting region, a display region surrounding the transmission region, and a periphery region surrounding the display region. The protection layer is disposed on the buffer layer. The active array is disposed on the buffer layer. The pixel array is disposed on the active array and electrically connected to the active array. The alignment film is conformally disposed on the protection layer and the second substrate. The alignment film includes a first portion in direct contact with the second substrate. A vertical projection of the first portion of the alignment film overlaps the transmitting region of the first substrate.

公开(公告)号：US11010584B2

公开(公告)日：2021-05-18

申请号：US16443834

申请日：2019-06-17

Applicant: Au Optronics Corporation

Inventor： Shin-Shueh Chen ,  Che-Chia Chang ,  Shu-Wen Tzeng ,  Yi-Wei Chen ,  Pao-Yu Huang

IPC: G09G5/00 ,  G06K9/00 ,  G06F3/042 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1333

Abstract: A display device includes a pixel array substrate, a sensing element substrate, and a display medium layer. The display medium layer is disposed between the pixel array substrate and the sensing element substrate. The sensing element substrate includes a substrate, a switch element, an insulation layer, an electrically conductive layer, a signal line, a sensing layer, and an electrode layer. The switch element is disposed on the substrate. The insulation layer covers the switch element. The electrically conductive layer is disposed on the insulation layer. The signal line is electrically connected to the electrically conductive layer. The sensing layer covers a top surface of the electrically conductive layer, a first side of the electrically conductive layer, and a second side of the electrically conductive layer. The electrode layer covers the sensing layer. The electrode layer is electrically connected to the switching element.

公开(公告)号：US20190057980A1

公开(公告)日：2019-02-21

申请号：US16166169

申请日：2018-10-22

Applicant: Au Optronics Corporation

Inventor： Chih-Chung Su ,  Po-Hsueh Chen ,  Yi-Wei Chen ,  Hsiu-Chun Hsieh

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L29/78633

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

公开(公告)号：US10128273B2

公开(公告)日：2018-11-13

申请号：US15099613

申请日：2016-04-15

Applicant: Au Optronics Corporation

Inventor： Chih-Chung Su ,  Po-Hsueh Chen ,  Yi-Wei Chen ,  Hsiu-Chun Hsieh

IPC: H01L27/12 ,  H01L29/786

Abstract: An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

公开(公告)号：US09082792B2

公开(公告)日：2015-07-14

申请号：US14092953

申请日：2013-11-28

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L27/12 ,  H01L27/28 ,  H01L29/786 ,  H01L51/00

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

公开(公告)号：US20220254968A1

公开(公告)日：2022-08-11

申请号：US17371069

申请日：2021-07-08

Applicant: Au Optronics Corporation

Inventor： Hsin-Hung Sung ,  Yi-Wei Chen

IPC: H01L33/62 ,  H01L33/00

Abstract: An electronic device, including an active device substrate, an insulation film, a vertical wire, and an anisotropic conductive adhesive, is provided. The active device substrate includes a substrate, a first wire, and a second wire. The first wire is configured on a first surface of the substrate, the second wire is configured on a second surface of the substrate, and a side surface connects the first surface to the second surface that is opposite to the first surface. The insulation film is configured on the side surface of the substrate. The vertical wire is configured on a surface of the insulation film and is located between the insulation film and the side surface of the substrate. The anisotropic conductive adhesive is configured between the vertical wire and the side surface of the substrate and electrically connects the vertical wire to the first wire and the second wire.

公开(公告)号：US20150255516A1

公开(公告)日：2015-09-10

申请号：US14720997

申请日：2015-05-26

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L27/28 ,  H01L21/441 ,  H01L51/05 ,  H01L51/00 ,  H01L21/467 ,  H01L29/66

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

公开(公告)号：US20140087525A1

公开(公告)日：2014-03-27

申请号：US14092953

申请日：2013-11-28

Applicant: Au Optronics Corporation

Inventor： Chung-Tao Chen ,  Ta-Wei Chiu ,  Yu-Pu Lin ,  Yi-Wei Chen

IPC: H01L29/66

CPC classification number: H01L27/286 ,  H01L21/441 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/281 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0053 ,  H01L51/0068 ,  H01L51/0072 ,  H01L51/0545

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract translation: CMOS晶体管的制造方法包括以下步骤。 在基板上形成第一栅极和第二栅极。 栅极绝缘体形成在衬底上以覆盖第一和第二栅极。 第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。 第一个源极和第一个漏极位于第一个栅极之上。 第二源极和第二漏极位于第二栅极之上。 在栅极绝缘体上形成第一沟道层和掩模层。 掩模层位于第一通道层上。 第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。 在栅极绝缘体上形成第二沟道层。 第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

公开(公告)号：US20200034599A1

公开(公告)日：2020-01-30

申请号：US16443834

申请日：2019-06-17

Applicant: Au Optronics Corporation

Inventor： Shin-Shueh Chen ,  Che-Chia Chang ,  Shu-Wen Tzeng ,  Yi-Wei Chen ,  Pao-Yu Huang

IPC: G06K9/00 ,  H01L27/12 ,  G06F3/042

Abstract: A display device includes a pixel array substrate, a sensing element substrate, and a display medium layer. The display medium layer is disposed between the pixel array substrate and the sensing element substrate. The sensing element substrate includes a substrate, a switch element, an insulation layer, an electrically conductive layer, a signal line, a sensing layer, and an electrode layer. The switch element is disposed on the substrate. The insulation layer covers the switch element. The electrically conductive layer is disposed on the insulation layer. The signal line is electrically connected to the electrically conductive layer. The sensing layer covers a top surface of the electrically conductive layer, a first side of the electrically conductive layer, and a second side of the electrically conductive layer. The electrode layer covers the sensing layer. The electrode layer is electrically connected to the switching element.

公开(公告)号：US10276600B2

公开(公告)日：2019-04-30

申请号：US15626306

申请日：2017-06-19

Applicant: AU Optronics Corporation

Inventor： Chu-Hsuan I ,  Yi-Wei Chen

IPC: H01L27/12

Abstract: A pixel structure includes a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The second metal layer is disposed on the first insulating layer, and the second metal layer includes at least one first data line, at least one source, and at least one first drain, wherein the first data line is electrically connected to the source. The second insulating layer is disposed on the second metal layer, the second insulating layer includes at least one opening that is disposed corresponding to the first drain, and the area of the opening is greater than the area of the first drain. The third metal layer includes at least one second drain that is electrically connected to the first drain, the second drain is disposed corresponding to the opening and disposed on the first drain.