公开(公告)号：US20210390995A1

公开(公告)日：2021-12-16

申请号：US16900470

申请日：2020-06-12

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G11C11/16

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory cells arranged in rows and columns, a plurality of word lines with each connected to a respective row of the memory cells along a row direction, a plurality of bit lines with each connected to a respective column of the memory cells along a column direction; a column decoder connected to the bit lines; a plurality of sense amplifiers connected to the column decoder; and a plurality of sense amplifier control circuits. Each of the sense amplifiers is connected to a unique one of the sense amplifier control circuits. Each of the sense amplifier control circuits includes a current detector circuit for detecting a sensing current, a current booster circuit for boosting the sensing current, and a timer circuit for providing a delayed trigger for a respective one of the sense amplifiers connected thereto.

公开(公告)号：US20180330770A1

公开(公告)日：2018-11-15

申请号：US15594387

申请日：2017-05-12

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G11C11/16

CPC classification number: G11C11/1673

Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.

公开(公告)号：US20190013056A1

公开(公告)日：2019-01-10

申请号：US16131430

申请日：2018-09-14

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G11C11/16 ,  G11C13/00

Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a selection transistor coupled in series between first and second conductive lines. The method includes the steps of precharging the first conductive line; allowing the voltage of the first conductive line to decay toward zero by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level. The discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero.

公开(公告)号：US11610616B2

公开(公告)日：2023-03-21

申请号：US16900470

申请日：2020-06-12

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G11C11/00 ,  G11C11/16

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory cells arranged in rows and columns, a plurality of word lines with each connected to a respective row of the memory cells along a row direction, a plurality of bit lines with each connected to a respective column of the memory cells along a column direction; a column decoder connected to the bit lines; a plurality of sense amplifiers connected to the column decoder; and a plurality of sense amplifier control circuits. Each of the sense amplifiers is connected to a unique one of the sense amplifier control circuits. Each of the sense amplifier control circuits includes a current detector circuit for detecting a sensing current, a current booster circuit for boosting the sensing current, and a timer circuit for providing a delayed trigger for a respective one of the sense amplifiers connected thereto.

公开(公告)号：US09921782B2

公开(公告)日：2018-03-20

申请号：US15011344

申请日：2016-01-29

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/0802 ,  G11C11/16

CPC classification number: G06F3/0679 ,  G06F3/061 ,  G06F3/0656 ,  G06F12/0802 ,  G06F2212/2024 ,  G06F2212/60 ,  G11C7/10 ,  G11C7/22 ,  G11C11/1675

Abstract: The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.

公开(公告)号：US10832751B2

公开(公告)日：2020-11-10

申请号：US16176292

申请日：2018-10-31

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga ,  Ebrahim Abedifard

IPC: G11C13/00 ,  G11C11/16 ,  G11C11/00

Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.

公开(公告)号：US20200135250A1

公开(公告)日：2020-04-30

申请号：US16176292

申请日：2018-10-31

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga ,  Ebrahim Abedifard

IPC: G11C11/16

Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.

公开(公告)号：US10127960B1

公开(公告)日：2018-11-13

申请号：US15594387

申请日：2017-05-12

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673

Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a two-terminal selector coupled in series between first and second conductive lines. The method includes the steps of precharging at least the first conductive line to attain a potential drop across the memory cell that is sufficiently large to turn on the two-terminal selector; allowing the voltage of the first conductive line to decay by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level.

公开(公告)号：US20170220301A1

公开(公告)日：2017-08-03

申请号：US15011344

申请日：2016-01-29

Applicant: Avalanche Technology, Inc.

Inventor： Dean K. Nobunaga

IPC: G06F3/06 ,  G11C11/16 ,  G06F12/08

CPC classification number: G06F3/0679 ,  G06F3/061 ,  G06F3/0656 ,  G06F12/0802 ,  G06F2212/2024 ,  G06F2212/60 ,  G11C7/10 ,  G11C7/22 ,  G11C11/1675

Abstract: The present invention is directed to a magnetic memory device that emulates DRAM and provides a plug-in or drop-in replacement for DRAM. The memory device includes one or more magnetic memory banks for storing data; a controller configured to issue a dormant write command upon receiving a refresh command for recharging DRAM capacitors; and a memory cache for storing temporary data and configured to save the temporary data to the one or more magnetic memory banks upon receiving the dormant write command from the controller. The memory device may be compliant with at least one version of low power DDR (LPDDR) Specification or at least one version of DDR SDRAM Specification.