利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

57 条记录 (耗时 0.02 秒)

    Method and apparatus for rescheduling operations in a processor
    2.
    发明授权
    Method and apparatus for rescheduling operations in a processor 失效
    用于在处理器中重新调度操作的方法和装置

    公开(公告)号：US07502912B2

    公开(公告)日：2009-03-10

    申请号：US10749272

    申请日：2003-12-30

    申请人： Avinash Sodani ,  Per H. Hammarlund ,  Stephan J. Jourdan

    发明人： Avinash Sodani ,  Per H. Hammarlund ,  Stephan J. Jourdan

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861

    摘要： A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting, and sorting the write order of instructions into the scheduler so that the duration the instructions sit idle in the scheduler is minimized. The analyses, prediction, and sorting may be done between an instruction queue and a scheduler by using delay units. The prediction can be based on history (latency, dependency, and resource) or on a general prediction scheme.

    摘要翻译： 一种用于在处理器中重新调度操作的方法和装置。 更具体地说，本发明涉及通过分析，预测和排序指令的写入顺序来最优化地使用处理器中的调度器资源，使得指令在调度器中空闲的持续时间最小化。 分析，预测和排序可以通过使用延迟单元在指令队列和调度器之间完成。 预测可以基于历史（延迟，依赖和资源）或一般预测方案。

    Method and system for transforming memory location references in instructions
    3.
    发明授权
    Method and system for transforming memory location references in instructions 有权
    在指令中转换内存位置引用的方法和系统

    公开(公告)号：US07174428B2

    公开(公告)日：2007-02-06

    申请号：US10745700

    申请日：2003-12-29

    申请人： Sebastien Hily ,  Per H. Hammarlund ,  Avinash Sodani

    发明人： Sebastien Hily ,  Per H. Hammarlund ,  Avinash Sodani

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3842 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3861

    摘要： Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store. In another embodiment of the present invention, the processor may re-execute the load instruction without memory renaming if the predicted store identifier does not match the identifier associated with the identified source store.

    摘要翻译： 本发明的实施例提供了一种用于存储器重命名的方法，装置和系统。 在一个实施例中，解码单元可以解码加载指令。 如果加载指令被预测为存储器重新命名，则加载指令可以具有与加载指令相关联的预测存储标识符。 解码单元可以将预测为被重命名的存储器的加载指令变换为数据移动指令和加载检查指令。 数据移动指令可以基于预测的存储标识符从高速缓存读取数据，并且加载检查指令可以将与所识别的源存储器相关联的标识符与预测的存储标识符进行比较。 如果预测的商店标识符与与所标识的源商店相关联的标识符匹配，则退休单元可以退出加载指令。 在本发明的另一个实施例中，如果预测的存储标识符与与所识别的源存储器相关联的标识符不匹配，则处理器可以重新执行加载指令而不进行存储器重命名。

    Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
    4.
    发明授权
    Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions 有权
    用于动态和静态预测指令资源利用率以生成执行集群分区的多级方案

    公开(公告)号：US07562206B2

    公开(公告)日：2009-07-14

    申请号：US11323043

    申请日：2005-12-30

    申请人： Avinash Sodani ,  Alexandre J. Farcy ,  Stephan J. Jourdan ,  Per Hammarlund ,  Mark C. Davis

    发明人： Avinash Sodani ,  Alexandre J. Farcy ,  Stephan J. Jourdan ,  Per Hammarlund ,  Mark C. Davis

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30101 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891

    摘要： Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations. Execution of a second set of micro-operations is predicted to involve execution resources to perform branching operations but not to perform memory access operations. The micro-operations are partitioned for execution in accordance with these predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources. The first and second sets of micro-operations are executed out of sequential order and are retired to represent their sequential instruction ordering.

    摘要翻译： 公开了用于预测执行群集并促进群集间通信的微架构策略和结构。 在所公开的实施例中，顺序排序的指令被解码成微操作。 预计执行一组微操作涉及执行资源以执行存储器访问操作和集群间通信，但不执行分支操作。 预计第二组微操作的执行涉及执行资源以执行分支操作，但不执行存储器访问操作。 根据这些预测将微操作划分为执行，即第一组执行资源的第一组微操作和第二组执行资源的第二组微操作。 第一组和第二组微操作按顺序执行，并退出以表示其顺序指令排序。

    Register alias table cache to map a logical register to a physical register
    5.
    发明授权
    Register alias table cache to map a logical register to a physical register 有权
    注册别名表缓存将逻辑寄存器映射到物理寄存器

    公开(公告)号：US07711898B2

    公开(公告)日：2010-05-04

    申请号：US10737760

    申请日：2003-12-18

    申请人： Avinash Sodani ,  Stephan J. Jourdan ,  Samie B. Samaan

    发明人： Avinash Sodani ,  Stephan J. Jourdan ,  Samie B. Samaan

    IPC分类号： G06F12/00

    CPC分类号： G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache.

    摘要翻译： 本发明的实施例涉及一种用于实现计算机处理器的寄存器转换表的功能的系统和方法，与已知布置相比，其面积要求减小。 在一个实施例中，装置可以包括寄存器别名表高速缓存以将逻辑寄存器映射到物理寄存器。 寄存器别名表缓存可以具有对应于体系结构逻辑寄存器子集的容量。 如果与逻辑寄存器对应的高速缓存条目从高速缓存中逐出，则该设备还可以包括耦合到高速缓存的存储逻辑，以执行操作以保存物理寄存器的现有内容。 该装置还可以包括耦合到高速缓存的负载逻辑，以执行将内容加载到物理寄存器的操作，并且如果高速缓存中不存在必需的映射，则在高速缓存中形成新的条目。