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    Determination of cache entry for future operation
    3.
    发明申请
    Determination of cache entry for future operation 有权
    确定高速缓存条目以供将来操作

    公开(公告)号：US20060230228A1

    公开(公告)日：2006-10-12

    申请号：US11100273

    申请日：2005-04-06

    申请人： Samie Samaan ,  Avinash Sodani

    发明人： Samie Samaan ,  Avinash Sodani

    IPC分类号： G06F12/00

    CPC分类号： G06F12/123

    摘要： A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K layers M/2 decision cells of a first layer to indicate the other one of the respective two of the M cache entries and to transmit a hit signal in response to the signal, a second layer of M/4 decision cells to enable the other one of the respective two of the M/2 decision cells of the first layer and transmit a second hit signal in response to the signal, a (K-1)th layer of two decision cells to enable the other one of the respective two decision cells of the (K-2)th layer and transmit a third hit signal in response to the second hit signal, and a Kth layer of a root decision cell to enable the other one of the respective two decision cells of the (K-1)th layer in response to the third hit signal.

    摘要翻译： 系统可以包括M个高速缓存条目，M个高速缓存条目中的每一个用于发送指示从高速缓存条目读取或写入的信号，并且包括数据寄存器和存储器地址寄存器以及K层决策单元，其中K = 日志2 M。 第一层的K层M / 2决定单元指示M个高速缓存条目中相应两个的另一个，并且响应于该信号发送命中信号，第二层M / 4个决定单元， 第一层的M / 2个决定单元中的相应两个中的另一个，并且响应于该信号发送第二命中信号，两个决定单元的第（K-1）层，以使得相应的两个 （K-2）层的决策单元，并且响应于第二命中信号发送第三命中信号，以及根决策单元的第K层，以使得（K-2）层的相应两个决定单元中的另一个能够执行， 1）层响应于第三命中信号。

    Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
    4.
    发明授权
    Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions 有权
    用于动态和静态预测指令资源利用率以生成执行集群分区的多级方案

    公开(公告)号：US07562206B2

    公开(公告)日：2009-07-14

    申请号：US11323043

    申请日：2005-12-30

    申请人： Avinash Sodani ,  Alexandre J. Farcy ,  Stephan J. Jourdan ,  Per Hammarlund ,  Mark C. Davis

    发明人： Avinash Sodani ,  Alexandre J. Farcy ,  Stephan J. Jourdan ,  Per Hammarlund ,  Mark C. Davis

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30101 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891

    摘要： Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations. Execution of a second set of micro-operations is predicted to involve execution resources to perform branching operations but not to perform memory access operations. The micro-operations are partitioned for execution in accordance with these predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources. The first and second sets of micro-operations are executed out of sequential order and are retired to represent their sequential instruction ordering.

    摘要翻译： 公开了用于预测执行群集并促进群集间通信的微架构策略和结构。 在所公开的实施例中，顺序排序的指令被解码成微操作。 预计执行一组微操作涉及执行资源以执行存储器访问操作和集群间通信，但不执行分支操作。 预计第二组微操作的执行涉及执行资源以执行分支操作，但不执行存储器访问操作。 根据这些预测将微操作划分为执行，即第一组执行资源的第一组微操作和第二组执行资源的第二组微操作。 第一组和第二组微操作按顺序执行，并退出以表示其顺序指令排序。

    Method and system for memory renaming
    5.
    发明申请
    Method and system for memory renaming 有权
    用于内存重命名的方法和系统

    公开(公告)号：US20050149702A1

    公开(公告)日：2005-07-07

    申请号：US10745700

    申请日：2003-12-29

    申请人： Sebastien Hily ,  Per Hammarlund ,  Avinash Sodani

    发明人： Sebastien Hily ,  Per Hammarlund ,  Avinash Sodani

    IPC分类号： G06F9/00 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

    CPC分类号： G06F9/3842 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3861

    摘要： Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store. In another embodiment of the present invention, the processor may re-execute the load instruction without memory renaming if the predicted store identifier does not match the identifier associated with the identified source store.

    摘要翻译： 本发明的实施例提供了一种用于存储器重命名的方法，装置和系统。 在一个实施例中，解码单元可以解码加载指令。 如果加载指令被预测为存储器重新命名，则加载指令可以具有与加载指令相关联的预测存储标识符。 解码单元可以将预测为被重命名的存储器的加载指令变换为数据移动指令和加载检查指令。 数据移动指令可以基于预测的存储标识符从高速缓存读取数据，并且加载检查指令可以将与所识别的源存储器相关联的标识符与预测的存储标识符进行比较。 如果预测的商店标识符与与所标识的源商店相关联的标识符匹配，则退休单元可以退出加载指令。 在本发明的另一个实施例中，如果预测的存储标识符与与所识别的源存储器相关联的标识符不匹配，则处理器可以重新执行加载指令而不进行存储器重命名。

    Flow optimization and prediction for VSSE memory operations
    8.
    发明申请
    Flow optimization and prediction for VSSE memory operations 有权
    VSSE存储器操作的流优化和预测

    公开(公告)号：US20070143575A1

    公开(公告)日：2007-06-21

    申请号：US11315964

    申请日：2005-12-21

    申请人： Stephen Jourdan ,  Per Hammarlund ,  Michael Fetterman ,  Michael Cornaby ,  Glenn Hinton ,  Avinash Sodani

    发明人： Stephen Jourdan ,  Per Hammarlund ,  Michael Fetterman ,  Michael Cornaby ,  Glenn Hinton ,  Avinash Sodani

    IPC分类号： G06F15/00

    CPC分类号： G06F9/345 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3844

    摘要： In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instruction to operate on a vector if the instruction is predicted to be unmasked and unit-stride, the instruction to access elements in memory, and accessing via the optimized μop flow two or more of the elements at the same time without determining masks of the two or more elements. Other embodiments are also described.

    摘要翻译： 在一个实施例中，公开了一种用于向量流单个指令，多数据（SIMD）扩展（VSSE）存储器操作的流优化和预测的方法。 该方法包括：如果预测指令是未屏蔽和单步的，则生成用于对矢量进行操作的指令的优化的微操作（muop）流程，访问存储器中的元件的指令以及经由优化的muop流2访问 或更多的元素，而不确定两个或更多个元件的掩模。 还描述了其它实施例。

    Staggered execution stack for vector processing
    9.
    发明申请
    Staggered execution stack for vector processing 有权
    用于矢量处理的交错执行堆栈

    公开(公告)号：US20070079179A1

    公开(公告)日：2007-04-05

    申请号：US11240982

    申请日：2005-09-30

    申请人： Stephan Jourdan ,  Avinash Sodani ,  Michael Fetterman ,  Per Hammarlund ,  Ronak Singhal ,  Glenn Hinton

    发明人： Stephan Jourdan ,  Avinash Sodani ,  Michael Fetterman ,  Per Hammarlund ,  Ronak Singhal ,  Glenn Hinton

    IPC分类号： G06F11/00

    CPC分类号： G06F9/3001 ,  G06F9/3012 ,  G06F9/3885

    摘要： In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and executing the operation on high order portions of the first and second source operands using a second execution stack of the processor, where the operation in the second execution stack is staggered by one or more cycles from the operation in the first execution stack. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种使用处理器的第一执行堆栈来执行第一和第二源操作数的低阶部分的操作的方法，并且使用第二和第二源操作数对第一和第二源操作数的高阶部分执行操作 处理器的执行堆栈，其中第二执行堆栈中的操作与第一执行堆栈中的操作交错一个或多个周期。 描述和要求保护其他实施例。