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公开(公告)号：US20250047315A1
公开(公告)日：2025-02-06
申请号：US18363243
申请日：2023-08-01
Inventor： Douglas S. Jansen , Sean Sengele , Marc A. Fisher , Gregory M. Flewelling , Curtis M. Grens
IPC: H04B1/3805 , H04B1/04
Abstract: A communications circuit includes a first circuit block and a second circuit block. The first circuit block includes a first splitter, a first signal path coupled to a first output of the first splitter, a second signal path coupled to a second output of the first splitter, and a first switch configured to couple the second signal path to a third signal path or to couple a fourth signal path to the third signal path. The second circuit block includes a second splitter, a fifth signal path coupled to a first output of the second splitter, a sixth signal path coupled to a second output of the second splitter, and a second switch configured to couple the sixth signal path to the third signal path or to couple a seventh signal path to the third signal path. The third signal path extends between the first and second circuit blocks.
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公开(公告)号：US11005424B2
公开(公告)日：2021-05-11
申请号：US16453152
申请日：2019-06-26
Inventor： Kathiravan Krishnamurthi , Souleymane Gnanou , Douglas S. Jansen
Abstract: A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.
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Patent Agency Ranking
公开(公告)号：US20200014371A1
公开(公告)日：2020-01-09
申请号：US16029118
申请日：2018-07-06
Inventor： Douglas S. Jansen
Abstract: A voltage controlled oscillator (VCO) is disclosed to provide reduced phase noise at higher operating frequencies. A buffer-first VCO configured according to an embodiment includes multiple VCO core circuits configured to provide synchronously tuned oscillator signals. Each VCO core circuit is coupled to a summing node through a buffer circuit that generates uncorrelated phase noise such that the summing node provides a summation output of the oscillator signals with reduced phase noise. A multiplexer-less VCO configured according to an embodiment includes multiple buffer-first VCO circuits configured to provide oscillator signals covering a range of frequencies. Each buffer-first VCO circuit is controlled or selected by an enable signal. Buffer circuits are configured to select one of the buffer-first VCO circuits for coupling to a transmission line during a given time period based on the enable signal. The transmission line is terminated in a matched impedance at each end of the line.
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公开(公告)号：US20250030393A1
公开(公告)日：2025-01-23
申请号：US18354354
申请日：2023-07-18
Inventor： Jonathan P. Comeau , Douglas S. Jansen , Gary M. Madison
Abstract: An attenuator circuit includes a differential input having first and second inputs, and a differential output having first and second outputs. The attenuator circuit further includes a first transistor coupled between the first input and the first output, a second transistor coupled between the second input and the second output, a third transistor coupled between the first input and the second output, and a fourth transistor coupled between the second input and the first output. During a pass-through state, the first and second transistors are enabled, and the third and fourth transistors may be disabled. During an attenuation state, the first, second, third, and fourth transistors are all disabled. An attenuator network (e.g., T or Pi network) may have its differential input terminals coupled to the first and second inputs of the differential input, and its differential output terminals coupled to the first and second outputs of the differential output.
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公开(公告)号：US10778270B1
公开(公告)日：2020-09-15
申请号：US16675624
申请日：2019-11-06
Inventor： Douglas S. Jansen
IPC: H04B1/16 , H04B1/06 , H04B1/00 , H01L25/065 , H01L23/66 , H01L23/538 , H01Q21/00 , H01Q5/314
Abstract: A communications receiver. One example embodiment is a system-in-package (SIP) device, which includes a three-dimensional interposer, a first bandpass filter integrated into the three-dimensional interposer, a first integrated circuit chip on the three-dimensional interposer, a second integrated circuit chip on the three-dimensional interposer, a second bandpass filter integrated into the three-dimensional interposer, and a third bandpass filter integrated into the three-dimensional interposer. The first integrated circuit chip includes a balanced amplifier that receives a first filtered signal and suppress distortion products. The second integrated circuit chip includes a first mixer and a second mixer. The first mixer receives an output of the balanced amplifier and mixes the output with a first oscillator signal. The second bandpass filter receives an output from the first mixer and generates a second filtered signal. The second mixer receives the second filtered signal and mixes the second filtered signal with a second oscillator signal.
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公开(公告)号：US10720906B2
公开(公告)日：2020-07-21
申请号：US16029118
申请日：2018-07-06
Inventor： Douglas S. Jansen
Abstract: A voltage controlled oscillator (VCO) is disclosed to provide reduced phase noise at higher operating frequencies. A buffer-first VCO configured according to an embodiment includes multiple VCO core circuits configured to provide synchronously tuned oscillator signals. Each VCO core circuit is coupled to a summing node through a buffer circuit that generates uncorrelated phase noise such that the summing node provides a summation output of the oscillator signals with reduced phase noise. A multiplexer-less VCO configured according to an embodiment includes multiple buffer-first VCO circuits configured to provide oscillator signals covering a range of frequencies. Each buffer-first VCO circuit is controlled or selected by an enable signal. Buffer circuits are configured to select one of the buffer-first VCO circuits for coupling to a transmission line during a given time period based on the enable signal. The transmission line is terminated in a matched impedance at each end of the line.
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公开(公告)号：US10374552B1
公开(公告)日：2019-08-06
申请号：US15952868
申请日：2018-04-13
Inventor： Douglas S. Jansen
IPC: H03D7/14 , H01L27/06 , H04B1/16 , H01L21/8249 , H01L29/737
Abstract: A mixer device is disclosed, which is fabricated as a bipolar-complementary metal oxide semiconductor (BiCMOS) integrated circuit device, to provide improved linearity and dynamic range, at higher operating frequencies. A mixer device configured according to an embodiment includes a driver circuit comprising bipolar junction transistors (BJTs) to convert a local oscillator signal to a high slew-rate gate drive signal. The driver circuit is configured as a quasi-complementary driver employing NPN BJTs. The mixer device further includes a mixer circuit comprising CMOS field-effect transistors (FETs) configured to mix an input signal with the gate drive signal to generate an output signal through the application of the gate drive signal to the gate port of the CMOS FETs. The mixer device further includes a voltage biasing circuit to provide a biased body voltage to the FETs to allow overdriving to a negative voltage relative to the body voltage.
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