公开(公告)号：US20250047315A1

公开(公告)日：2025-02-06

申请号：US18363243

申请日：2023-08-01

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Douglas S. Jansen ,  Sean Sengele ,  Marc A. Fisher ,  Gregory M. Flewelling ,  Curtis M. Grens

IPC: H04B1/3805 ,  H04B1/04

Abstract: A communications circuit includes a first circuit block and a second circuit block. The first circuit block includes a first splitter, a first signal path coupled to a first output of the first splitter, a second signal path coupled to a second output of the first splitter, and a first switch configured to couple the second signal path to a third signal path or to couple a fourth signal path to the third signal path. The second circuit block includes a second splitter, a fifth signal path coupled to a first output of the second splitter, a sixth signal path coupled to a second output of the second splitter, and a second switch configured to couple the sixth signal path to the third signal path or to couple a seventh signal path to the third signal path. The third signal path extends between the first and second circuit blocks.

公开(公告)号：US09900012B2

公开(公告)日：2018-02-20

申请号：US15099753

申请日：2016-04-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Joseph D. Cali ,  Curtis M. Grens ,  Lawrence J. Kushner ,  Steven E. Turner

IPC: H03K21/00 ,  H03K23/00 ,  H03K21/02 ,  H03K21/38 ,  H03L7/197 ,  G06F7/68 ,  H03K23/40 ,  G06F1/08 ,  H03K23/64 ,  H03K21/40 ,  H03K23/58 ,  H03K23/68 ,  H03K21/10

CPC classification number: H03K21/026 ,  G06F1/08 ,  G06F7/68 ,  H03K21/00 ,  H03K21/10 ,  H03K21/38 ,  H03K21/40 ,  H03K23/00 ,  H03K23/40 ,  H03K23/58 ,  H03K23/64 ,  H03K23/68 ,  H03L7/1974

Abstract: Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

公开(公告)号：US20190058499A1

公开(公告)日：2019-02-21

申请号：US15677528

申请日：2017-08-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc

Inventor： Curtis M. Grens

IPC: H04B1/10 ,  H03G3/30 ,  H04K3/00

Abstract: Anti-jamming techniques are provided for RF receivers, such as those that operate in hostile environments. In some embodiments, the techniques are embodied in an anti-jam communications system configured with automatic gain control (AGC) that is complementary. The system includes a first AGC circuit prior to an interference suppression circuit and a second AGC circuit after the interference suppression circuit. The first AGC circuit operates to adjust the power level presented to the interference suppression circuit to facilitate interference cancellation. The second AGC circuit operates to maintain the original power level of the desired communications signal and prevent amplitude errors as the first AGC circuit responds to fluctuations in jammer signal power. The second AGC can be slaved to the first AGC circuit such that the sum of two gain values is held constant, according to some embodiments. In this manner, the first and second AGC circuits provide a complementary-AGC system.

公开(公告)号：US10211863B1

公开(公告)日：2019-02-19

申请号：US15677528

申请日：2017-08-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc

Inventor： Curtis M. Grens

IPC: H04B1/10 ,  H04K3/00 ,  H03G3/30

Abstract: Anti-jamming techniques are provided for RF receivers, such as those that operate in hostile environments. In some embodiments, the techniques are embodied in an anti-jam communications system configured with automatic gain control (AGC) that is complementary. The system includes a first AGC circuit prior to an interference suppression circuit and a second AGC circuit after the interference suppression circuit. The first AGC circuit operates to adjust the power level presented to the interference suppression circuit to facilitate interference cancellation. The second AGC circuit operates to maintain the original power level of the desired communications signal and prevent amplitude errors as the first AGC circuit responds to fluctuations in jammer signal power. The second AGC can be slaved to the first AGC circuit such that the sum of two gain values is held constant, according to some embodiments. In this manner, the first and second AGC circuits provide a complementary-AGC system.

公开(公告)号：US11012079B1

公开(公告)日：2021-05-18

申请号：US16721494

申请日：2019-12-19

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Joseph D. Cali ,  Curtis M. Grens ,  Richard L. Harwood ,  Gary M. Madison

IPC: H03L7/099 ,  H03L7/107 ,  H03L7/093

Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

公开(公告)号：US10079607B1

公开(公告)日：2018-09-18

申请号：US15689736

申请日：2017-08-29

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Curtis M. Grens ,  Justin A. Cartwright ,  Gregory M. Flewelling ,  Richard L. Harwood ,  James M. Meredith

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/10

CPC classification number: H03L7/093 ,  H03L7/099 ,  H03L7/103 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/50

Abstract: Techniques are provided for phase-locked loop (PLL) configuration, based on a calibrated lookup table (LUT). A methodology implementing the techniques according to an embodiment includes selecting one of a number of voltage controlled oscillators (VCOs) of the PLL, and selecting a tuning parameter to control the VCO. The method further includes testing the PLL, using multiple loop divider values, to determine a minimum and maximum value that define the lower and upper bounds of a range of loop divider values for which the PLL achieves a locked state while using the selected VCO and tuning parameter. The method further includes storing PLL configuration parameters to an entry in the configuration LUT, the PLL configuration parameters to include an identification of the selected VCO, the selected tuning parameter, the minimum loop divider value, and the maximum loop divider value. The method iterates using additional combinations of selected VCOs and tuning parameters.