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公开(公告)号：US20240353950A1
公开(公告)日：2024-10-24
申请号：US18251172
申请日：2022-05-31
发明人： Mengyang WEN , Guangliang SHANG , Shiming SHI , Hao LIU , Li WANG , Libin LIU , Hui ZHAO , Chunyan LI
CPC分类号： G06F3/04164 , G06F3/0412 , G06F3/0446 , H10K59/40 , G06F2203/04111
摘要： A touch display panel has a display area and a fan-out area located at a side of the display area. The display area includes a first display region and a second display region located around the first display region. The touch display panel includes a display substrate and a touch function layer. The display substrate has a display side, and the touch function layer is located on the display side of the display substrate. The touch function layer includes a plurality of touch electrodes and a plurality of touch leads. The plurality of touch electrodes are located in the first display region, and the plurality of touch leads are electrically connected to the plurality of touch electrodes and extend to the fan-out area through the second display region.
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2.发明公开公开(公告)号：US20240290260A1
公开(公告)日：2024-08-29
申请号：US18043467
申请日：2022-02-24
发明人： Guangliang SHANG , Li WANG , Baoyun WU , Xiyu ZHAO , Yu FENG , Libin LIU , Shiming SHI
IPC分类号： G09G3/3233
CPC分类号： G09G3/3233 , G09G2310/08 , G09G2320/0247 , G09G2320/0271 , G09G2330/021
摘要： A parameter adjustment method of a display module includes: setting an initial value of a light-emitting delay time and specified gray levels; based on the initial value of the light-emitting delay time, adjusting the light-emitting delay time stepwise until a value of an adjusted light-emitting delay time exceeds a preset range of the light-emitting delay time, so that values of the light-emitting delay time within the preset range of the light-emitting delay time are obtained; obtaining flicker values of the display module at the specified gray levels for each value of the light-emitting delay time; and determining a preferred value of the light-emitting delay time from the values of the light-emitting delay time according to flicker values corresponding to the values of the light-emitting delay time.
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公开(公告)号：US20240194141A1
公开(公告)日：2024-06-13
申请号：US18581023
申请日：2024-02-19
发明人： Libin LIU , Mei LI , Hongli WANG
IPC分类号： G09G3/3233 , H01L27/12 , H10K59/121 , H10K59/131
CPC分类号： G09G3/3233 , H10K59/131 , G09G2300/0426 , G09G2300/0443 , G09G2300/0452 , G09G2300/0819 , G09G2300/0852 , G09G2320/0233 , H01L27/124 , H10K59/1213
摘要： A display substrate, a preparation method thereof, a display panel, and a display device are provided. The display substrate includes a base substrate and a repeating unit, the repeating unit includes a plurality of sub-pixels including a first sub-pixel and a second sub-pixel, a color of light emitted by a light-emitting element of the first sub-pixel is identical to a color of light emitted by a light-emitting element of the second sub-pixel, a shape of a first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel is different from a shape of a first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel.
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公开(公告)号：US20240179985A1
公开(公告)日：2024-05-30
申请号：US17773595
申请日：2021-04-01
IPC分类号： H10K59/131
CPC分类号： H10K59/1315
摘要： The present disclosure is related to an array substrate and a display device. The array substrate has a display area and a peripheral area surrounding the display area. The array substrate includes a gate material layer and a source and drain material layer that are sequentially stacked on a base substrate. The array substrate further includes a driving signal line. The driving signal line includes a first sub-signal line and a second sub-signal line. The first sub-signal line is arranged in the gate material layer and extends from the peripheral area to the display area. The second sub-signal line is arranged in the source and drain material layer and located at least in the display area. The first sub-signal line and the second sub-signal line are electrically connected through a via hole.
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公开(公告)号：US20240169924A1
公开(公告)日：2024-05-23
申请号：US17778916
申请日：2021-06-18
发明人： Guangliang SHANG , Libin LIU , Mengyang WEN , Jiangnan LU , Li WANG , Long HAN
IPC分类号： G09G3/3266 , G09G3/3233 , H10K59/131
CPC分类号： G09G3/3266 , G09G3/3233 , H10K59/131 , G09G2300/0426 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/0286 , G09G2310/08 , G09G2320/0233 , G09G2320/0257 , G09G2330/021
摘要： The embodiments of the present disclosure provides a display substrate, including: an active region and a peripheral region, the active region is provided therein with a plurality of pixel units arranged in an array, all the pixel units are divided into n pixel unit groups, the peripheral region is provided therein with a driver block including a first gate drive circuit having n+x first signal output terminals configured to sequentially output first gate drive signals in an active level and the first gate line provided for an ith pixel unit group is electrically connected to a (i+x)th first signal output terminal, and the reset signal line provided for the ith pixel unit group is electrically connected to an ith first signal output terminal, with i being a positive integer and i≤n.
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公开(公告)号：US20240144885A1
公开(公告)日：2024-05-02
申请号：US17771016
申请日：2021-05-27
发明人： Long HAN , Guangliang SHANG , Libin LIU
IPC分类号： G09G3/3266 , G11C19/28
CPC分类号： G09G3/3266 , G11C19/28 , G09G2310/0286 , G09G2310/08 , G09G2330/021
摘要： Disclosed is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, the gate drive circuit includes a plurality of cascaded shift register units, and a shift register unit is connected with at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected with a first group of clock signal lines, and the second output circuit is connected with the first group of clock signal lines and a second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit.
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公开(公告)号：US20240105119A1
公开(公告)日：2024-03-28
申请号：US17637815
申请日：2021-04-23
发明人： Libin LIU , Li WANG , Guangliang SHANG , Yu FENG , Long HAN , Baoyun WU , Shiming SHI
IPC分类号： G09G3/3233
CPC分类号： G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2320/0233 , G09G2340/0435
摘要： A pixel circuit, a driving method therefor and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a leak-proof sub-circuit, a storage sub-circuit and a light-emitting element. The reset sub-circuit is configured to reset a fourth node under control of a signal of a light-emitting control signal terminal and reset a fifth node under control of a signal of a reset control signal terminal. The compensation sub-circuit is configured to compensate a threshold voltage of the driving sub-circuit to the fifth node under the control of a signal of a first scanning signal terminal. The leak-proof sub-circuit is configured to write a signal of the fifth node into a first node under control of a signal of a second scanning signal terminal.
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公开(公告)号：US20230419878A1
公开(公告)日：2023-12-28
申请号：US18466619
申请日：2023-09-13
发明人： Guangliang SHANG , Jie ZHANG , Jiangnan LU , Mei LI , Libin LIU
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G2300/0426 , G09G2300/0842 , G09G2310/0267 , G09G2330/021
摘要： A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit controls to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit controls to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal.
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公开(公告)号：US20230180551A1
公开(公告)日：2023-06-08
申请号：US17923934
申请日：2021-11-04
发明人： Jiangnan LU , Libin LIU , Guangliang SHANG , Long HAN , Yu FENG , Li WANG , Mei LI
IPC分类号： H10K59/131 , H10K59/12
CPC分类号： H10K59/131 , H10K59/1201 , H10K59/124
摘要： A display panel includes: a substrate; at least one first signal line disposed on the substrate and located in a peripheral region; at least one second signal line disposed on the substrate and located in the peripheral region; an insulating layer covering the at least one first signal line and the at least one second signal line; and a shielding signal line covering the at least one groove. The at least one second signal line and the at least one first signal line are arranged in a same layer. A surface of the insulating layer away from the substrate has at least one groove. An orthogonal projection, on the substrate, of a bottom surface of a groove is located between orthogonal projections, on the substrate, of a first signal line and a second signal line.
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公开(公告)号：US20230020923A1
公开(公告)日：2023-01-19
申请号：US17948576
申请日：2022-09-20
发明人： Yipeng CHEN , Lujiang HUANGFU , Libin LIU
IPC分类号： H01L27/32 , G09G3/3233
摘要： A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.
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