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公开(公告)号:US20250022884A1
公开(公告)日:2025-01-16
申请号:US18276646
申请日:2022-07-14
Inventor: Quanzhou LIU , Haijiao QIAN , Liang CHEN , Zexu LIU
IPC: H01L27/12 , G02F1/1335 , G02F1/1362
Abstract: Provided is an array substrate, including: a substrate; a first insulating layer and a second insulating layer that are successively stacked; a first electrode disposed on a side, proximal to the substrate, of the first insulating layer; a second electrode disposed between the first insulating layer and the second insulating layer; and a lap electrode disposed on a side, distal from the substrate, of the second insulating layer. The array substrate includes a plurality of first vias and a plurality of second vias. The lap electrode is electrically connected to the first electrode and is electrically connected to the second electrode. An orthographic projection of the first electrode on the substrate is overlapped with an orthographic projection of the second electrode on the substrate, and covers a region between at least one of the first vias and at least one of the second vias.
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公开(公告)号:US20240242659A1
公开(公告)日:2024-07-18
申请号:US18005373
申请日:2021-11-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Li XIAO , Seungwoo HAN , Dongni LIU , Haoliang ZHENG , Minghua XUAN , Jiao ZHAO , Liang CHEN , Xiaorong CUI
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0861 , G09G2310/0251 , G09G2310/0262 , G09G2310/0297
Abstract: A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.
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公开(公告)号:US20230043192A1
公开(公告)日:2023-02-09
申请号:US17789193
申请日:2021-08-16
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Liang CHEN , Ke WANG , Haoliang ZHENG , Minghua XUAN , Dongni LIU , Hao CHEN , Qi QI
IPC: H01L27/12 , H01L25/16 , H01L23/00 , G09G3/3233
Abstract: A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.
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公开(公告)号:US20230013848A1
公开(公告)日:2023-01-19
申请号:US17783207
申请日:2021-05-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Lubin SHI , Wanpeng TENG , Liang CHEN , Bin QIN , Ke WANG , Jintao PENG , Fangzhen ZHANG , Kuanjun PENG
IPC: H01L27/32
Abstract: A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.
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公开(公告)号:US20220406245A1
公开(公告)日:2022-12-22
申请号:US17642025
申请日:2021-04-08
Applicant: BOE Technology Group Co., Ltd.
Inventor: Hao CHEN , Zhenyu ZHANG , Jiao ZHAO , Li XIAO , Dongni LIU , Haoliang ZHENG , Liang CHEN , Minghua XUAN , Ming YANG , Xinhong LU , Qi QI
Abstract: An array substrate, a detection method for the array substrate, and a tiled display panel. In the array substrate, each of pixels (1) comprises sub-pixels (01) of at least three colors and a. pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) comprises at least one inorganic light-emitting diode; a display area (A1) further comprises: a positive signal line (Tian) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Din), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.
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公开(公告)号:US20220335889A1
公开(公告)日:2022-10-20
申请号:US17760733
申请日:2021-03-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Haoliang ZHENG , Minghua XUAN , Dongni LIU , Zhenyu ZHANG , Li XIAO , Liang CHEN , Hao CHEN , Jiao ZHAO , Lijun YUAN , Yi OUYANG , Qi QI
IPC: G09G3/3233 , G11C19/28
Abstract: A shift register (SR) includes a voltage control circuit (110) and a bias compensation circuit (120). The voltage control circuit (110) is configured to control a voltage at a first node (Output) to be a first voltage or a second voltage. The bias compensation circuit (120) is configured to: when the voltage at the first node (Output) is the first voltage, transmit a first signal received by a first signal terminal (VDD-A) to a first signal output terminal (EM1), and transmit a second signal received by a second signal terminal (VDD-B) to a second signal output terminal (EM2); and in response to the voltage at the first node (Output) being the second voltage, transmit a signal received by a first voltage terminal (LVGL1) to the first signal output terminal (EM1) and the second signal output terminal (EM2).
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公开(公告)号:US20220293037A1
公开(公告)日:2022-09-15
申请号:US17511335
申请日:2021-10-26
Applicant: BOE Technology Group Co., Ltd.
Inventor: Haoliang ZHENG , Minghua XUAN , Dongni LIU , SeungWoo HAN , Li XIAO , Liang CHEN , Hao CHEN , Jiao ZHAO , Qi QI
IPC: G09G3/32
Abstract: Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.
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公开(公告)号:US20210366389A1
公开(公告)日:2021-11-25
申请号:US16491547
申请日:2019-03-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Dongni LIU , Minghua XUAN , Xiaochuan CHEN , Lei WANG , Zheng FANG , Li XIAO , Liang CHEN , Shengji YANG , Pengcheng LU
IPC: G09G3/3233
Abstract: A pixel driving circuit including: N pixel circuits each including a first node and a power supply terminal, N being an integer greater than 1; and N multiplexing circuits configured to selectively couple a data line to the first nodes of the N pixel circuits. A first one of the N multiplexing circuits includes a multiplexing control circuit, and a second one to an N-th one of the N multiplexing circuits include respective multiplexing control circuits and respective reset circuits. The reset circuit of a (j+1)-th one of the N multiplexing circuits is configured to reset the first node of a (j+1)-th one of the N pixel circuits with a power supply voltage in response to a j-th multiplexing control signal being active, j being an integer and 1≤j
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公开(公告)号:US20210358384A1
公开(公告)日:2021-11-18
申请号:US16614365
申请日:2019-04-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Dongni LIU , Minghua XUAN , Lei WANG , Xiaochuan CHEN , Liang CHEN , Li XIAO , Detao ZHAO , Shengji YANG , Pengcheng LU , Zheng FANG
IPC: G09G3/20
Abstract: The present disclosure relates to the field of display technologies, and in particular, to a shift register circuit and a display device. The shift register circuit may include a plurality of GOAs for outputting scan signals to a plurality of pixel driving circuits and a plurality of EOAs for outputting control signals to the plurality of pixel driving circuits, where the GOAs and the EOAs are alternately arranged in a straight line.
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公开(公告)号:US20210333654A1
公开(公告)日:2021-10-28
申请号:US16614343
申请日:2019-05-15
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Detao ZHAO , Li XIAO , Lei WANG , Dongni LIU , Liang CHEN , Jifeng TAN , Minghua XUAN , Xiaochuan CHEN
IPC: G02F1/1343 , F21V8/00 , G02F1/1335
Abstract: A display substrate includes: a plurality of sub-pixel regions at a first base substrate, each of the plurality of sub-pixel regions including a light-blocking region and aperture regions located at opposing sides of the light-blocking region; and a first transparent electrode and a second transparent electrode within each of the plurality of sub-pixel regions, configured to drive a liquid crystal layer; wherein the first transparent electrode includes a first electrode unit located inside the light-blocking region and including a plurality of first sub-electrodes, wherein each of the plurality of first sub-electrodes are separated from two adjacent first sub-electrodes by a separation distance; and wherein the separation distance between two adjacent first sub-electrodes nearest to a center line of the light-blocking region is smaller than the separation distance between two adjacent first sub-electrodes nearest to an edge of the light-blocking region
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