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    Array substrate, method of manufacturing the same, display panel and display device
    5.
    发明授权
    Array substrate, method of manufacturing the same, display panel and display device 有权

    公开(公告)号：US10365528B2

    公开(公告)日：2019-07-30

    申请号：US15801624

    申请日：2017-11-02

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Yoon-Sung Um

    IPC: G09G3/20 ,  G09G3/36 ,  G02F1/1362 ,  H01L27/12 ,  G02F1/1343

    Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same, a display panel and a display device. The array substrate includes: a plurality of pixel units, the plurality of pixel units being arranged in rows and columns and each row of the pixel units comprising a first sub-pixel row, a second sub-pixel row and a third sub-pixel row being adjacent successively; and a plurality of gate lines, each of the gate lines being configured to drive one sub-pixel row, and gate lines for driving the first sub-pixel row and the second sub-pixel row in a same pixel unit being located between the first sub-pixel row and the second sub-pixel row in the pixel unit.

    Array substrate comprising first and second common electrodes that are powered independently, its manufacturing method, and display device
    6.
    发明授权
    Array substrate comprising first and second common electrodes that are powered independently, its manufacturing method, and display device 有权
    阵列基板包括独立供电的第一和第二公共电极，其制造方法和显示装置

    公开(公告)号：US09323111B2

    公开(公告)日：2016-04-26

    申请号：US14105379

    申请日：2013-12-13

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Yoon-Sung Um ,  Hyun-Sic Choi ,  Zhiqiang Xu ,  Hui Li

    IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1362

    CPC classification number: G02F1/1343 ,  G02F1/134309 ,  G02F1/136 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/13606 ,  G02F2001/136218 ,  Y10T29/49117

    Abstract: The present invention provides an array substrate, its manufacturing method, and a display device. The array substrate comprises a plurality of grid lines a plurality of data lines, and pixel regions defined by every two adjacent grid Fines and every two adjacent data lines. The pixel region is provided with a common electrode, a pixel electrode and a thin film transistor. The common electrode includes a first common electrode and a second common electrode which are powered independently. A projection of the first common electrode onto a layer where the data lines are located covers the data line, and a projection of the second common electrode onto a layer where the pixel electrode is located falls on the pixel electrode.

    Abstract translation: 本发明提供阵列基板，其制造方法和显示装置。 阵列基板包括多个网格线，多条数据线，以及由每两个相邻网格细分和每两个相邻数据线定义的像素区域。 像素区域设置有公共电极，像素电极和薄膜晶体管。 公共电极包括独立供电的第一公共电极和第二公共电极。 第一公共电极到数据线所在的层的投影覆盖数据线，并且第二公共电极在像素电极所在的层上的投影落在像素电极上。

    Array substrate, display device and method for driving pixels within each pixel region of the array substrate
    7.
    发明授权
    Array substrate, display device and method for driving pixels within each pixel region of the array substrate 有权
    阵列基板，显示装置及驱动阵列基板的各像素区域内的像素的方法

    公开(公告)号：US09105248B2

    公开(公告)日：2015-08-11

    申请号：US14071823

    申请日：2013-11-05

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Yoon-Sung Um ,  Hyun-Sic Choi ,  Zhiqiang Xu ,  Hui Li

    IPC: G09G3/36

    CPC classification number: G09G3/3614 ,  G09G2300/0426 ,  G09G2320/0233

    Abstract: Embodiments of the present disclosure provide an array substrate comprising a plurality of gate lines, a plurality of data lines, and pixel regions each of which is defined by intersecting one gate line and two neighboring data lines among the plurality of gate lines and the plurality of data lines wherein two thin film transistors (TFTs) are formed at the intersections between the gate line and the two neighboring data lines in each pixel region, a first pixel electrode and a second pixel electrode are alternately arranged in each pixel region. A first thin film transistor of the two thin film transistors is coupled to the first pixel electrode, a second thin film transistor of the two thin film transistors is coupled to the second pixel electrode. The two neighboring data lines participating in defining a pixel region comprise a first data line coupling to the first thin film transistor and a second data line coupling to the second thin film transistor. Voltages having the same absolute value and opposite polarities are applied to the first pixel electrode and the second pixel electrode respectively via the first thin film transistor and the second thin film transistor.

    Abstract translation: 本公开的实施例提供了一种阵列基板，其包括多条栅极线，多条数据线和像素区域，每条栅极线路与多条栅极线路中的一条栅极线和两条相邻的数据线相交， 数据线，其中在每个像素区域中的栅极线和两个相邻数据线之间的交点处形成两个薄膜晶体管（TFT），第一像素电极和第二像素电极在每个像素区域中交替布置。 两个薄膜晶体管的第一薄膜晶体管耦合到第一像素电极，两个薄膜晶体管的第二薄膜晶体管耦合到第二像素电极。 参与定义像素区域的两个相邻数据线包括耦合到第一薄膜晶体管的第一数据线和耦合到第二薄膜晶体管的第二数据线。 具有相同绝对值和相反极性的电压分别经由第一薄膜晶体管和第二薄膜晶体管施加到第一像素电极和第二像素电极。

    Array substrate having common electrode that does not overlap with gate line, display panel and display device
    8.
    发明授权
    Array substrate having common electrode that does not overlap with gate line, display panel and display device 有权

    公开(公告)号：US10656488B2

    公开(公告)日：2020-05-19

    申请号：US15822091

    申请日：2017-11-24

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Liwei Liu ,  Yoon-Sung Um

    IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1335

    Abstract: The disclosure provides an array substrate, a display panel and a display device, and the array substrate includes: an insulation substrate, gate lines arranged on the insulation substrate to extend in a first direction, and data lines arranged on the insulation substrate to extend in a second direction, and to be insulated from the gate lines, the gate lines intersect with the data lines to define a plurality of pixel areas, each pixel area has a larger length in the first direction than that in the second direction, where the array substrate further includes a plurality of common electrodes, and a projection of each of the plurality of common electrodes on the insulation substrate and a projection of each of the gate lines on the insulation substrate do not overlap with each other.

    ARRAY SUBSTRATE, DISPLAY DEVICE AND PIXEL DRIVING METHOD
    9.
    发明申请
    ARRAY SUBSTRATE, DISPLAY DEVICE AND PIXEL DRIVING METHOD 有权
    阵列基板，显示装置和像素驱动方法

    公开(公告)号：US20140125571A1

    公开(公告)日：2014-05-08

    申请号：US14071823

    申请日：2013-11-05

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Yoon-Sung Um ,  Hyun-Sic Choi ,  Zhiqiang Xu ,  Hui Li

    IPC: G09G3/36

    CPC classification number: G09G3/3614 ,  G09G2300/0426 ,  G09G2320/0233

    Abstract: Embodiments of the present disclosure provide an array substrate comprising a plurality of gate lines, a plurality of data lines, and pixel regions each of which is defined by intersecting one gate line and two neighboring data lines among the plurality of gate lines and the plurality of data lines wherein two thin film transistors (TFTs) are formed at the intersections between the gate line and the two neighboring data lines in each pixel region, a first pixel electrode and a second pixel electrode are alternately arranged in each pixel region. A first thin film transistor of the two thin film transistors is coupled to the first pixel electrode, a second thin film transistor of the two thin film transistors is coupled to the second pixel electrode. The two neighboring data lines participating in defining a pixel region comprise a first data line coupling to the first thin film transistor and a second data line coupling to the second thin film transistor. Voltages having the same absolute value and opposite polarities are applied to the first pixel electrode and the second pixel electrode respectively via the first thin film transistor and the second thin film transistor.

    Abstract translation: 本公开的实施例提供了一种阵列基板，其包括多条栅极线，多条数据线和像素区域，每条栅极线路与多条栅极线路中的一条栅极线和两条相邻的数据线相交， 数据线，其中在每个像素区域中的栅极线和两个相邻数据线之间的交点处形成两个薄膜晶体管（TFT），第一像素电极和第二像素电极在每个像素区域中交替布置。 两个薄膜晶体管的第一薄膜晶体管耦合到第一像素电极，两个薄膜晶体管的第二薄膜晶体管耦合到第二像素电极。 参与定义像素区域的两个相邻数据线包括耦合到第一薄膜晶体管的第一数据线和耦合到第二薄膜晶体管的第二数据线。 具有相同绝对值和相反极性的电压分别经由第一薄膜晶体管和第二薄膜晶体管施加到第一像素电极和第二像素电极。

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