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公开(公告)号：US20190189234A1
公开(公告)日：2019-06-20
申请号：US16331004
申请日：2018-05-30
Inventor： Shuai CHEN , Zhi ZHANG , Xiuzhu TANG , Yuanbo ZHANG , Zhihui WANG , Qian QIAN , Lijun XIONG , Tao ZHOU , Xing DONG
CPC classification number: G11C19/287 , G09G3/20 , G09G3/36 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G11C19/28
Abstract: A shift register unit includes a first output control circuit, a first output circuit, a second output control circuit, a second output circuit, a reset circuit, and a node set circuit. The node set circuit is configured to periodically transfer a first voltage having an inactive level to a first node within the shift register unit during being enabled.
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公开(公告)号：US20180233210A1
公开(公告)日：2018-08-16
申请号：US15503830
申请日：2016-08-25
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Mingfu HAN , Guangliang SHANG , Yuanbo ZHANG , Yujie GAO , Yan YAN , Yingmeng MIAO , Seungwoo HAN , Zhihe JIN , Xing YAO , Haoliang ZHENG
CPC classification number: G11C19/287 , G09G3/20 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0286 , G11C19/28
Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.
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公开(公告)号：US20160049424A1
公开(公告)日：2016-02-18
申请号：US14402266
申请日：2013-12-10
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yuanbo ZHANG , Wei QIN , Seung Woo HAN , Ruoyu MA
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1259
Abstract: An array substrate, a manufacturing method of the array substrate and a display device including the array substrate are disclosed. The array substrate includes a substrate (1), a common electrode layer (401) located on the substrate (1) and a conductive layer (2) provided on a surface of the substrate (1), the conductive layer (2) and the common electrode layer (401) are electrically connected in parallel. The common electrode and the conductive layer are formed into a parallel structure, so that the resistance can be decreased, and in turn, crosstalk, greenish and other phenomenon of the array substrate are reduced, thereby promoting the picture quality of the display device.
Abstract translation: 公开了阵列基板，阵列基板的制造方法和包括阵列基板的显示装置。 阵列基板包括基板（1），位于基板（1）上的公共电极层（401）和设置在基板（1）的表面上的导电层（2），导电层（2）和 公共电极层（401）并联电连接。 公共电极和导电层形成为平行结构，从而可以降低电阻，从而降低阵列基板的串扰，绿色等现象，从而提高显示装置的图像质量。
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公开(公告)号：US20200286420A1
公开(公告)日：2020-09-10
申请号：US15774442
申请日：2017-10-19
Inventor： Yajie BAI , Zhuo XU , Yuanbo ZHANG , Yan FANG , Ming DENG , Zijie TANG , Jaikwang KIM
Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.
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公开(公告)号：US20190237037A1
公开(公告)日：2019-08-01
申请号：US16241689
申请日：2019-01-07
Inventor： Yuanbo ZHANG , Wenhao YOU , Rui XUE , Rui WANG , Pengyue ZHANG , Xiaolin WANG
IPC: G09G3/36
CPC classification number: G09G3/3688 , G09G3/3677 , G09G2300/0408 , G09G2310/08
Abstract: The present disclosure provides a display substrate such that each pixel unit of the display substrate includes a switching circuit and a control circuit, and the switching circuit is connected to a corresponding gate line, a control circuit of a respective pixel unit, and a corresponding pixel electrode. The control circuit is configured to transmit a data signal on a corresponding data line to a switching circuit of the respective pixel unit under control of a corresponding control signal line, and n is an integer not less than 2. The present disclosure further provides a display device including the above display substrate and a driving method for the above display substrate.
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Patent Agency Ranking
公开(公告)号：US20160042706A1
公开(公告)日：2016-02-11
申请号：US14423006
申请日：2014-05-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Seung Woo HAN , Yuanbo ZHANG , Yoon Sung UM
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G3/20 , G09G3/3685 , G09G2300/0408 , G09G2310/0275 , G09G2310/08 , G09G2370/14
Abstract: A data driving circuit comprises a plurality of driving units, each of the driving units comprising first, second, third and fourth switch units, each of the switch units comprising first and second input terminals and an output terminal; the output terminals being output terminals of the data driving circuit; two data control terminals, one of which is respectively connected to the first input terminals of the first switch unit and the second switch unit, the other of which is respectively connected to the first input terminals of the third switch unit and the fourth switch unit; a first switching control terminal, connected to the second input terminal of one of the switch units connected to the same data control terminal; a second switching control terminal, connected to the second input terminal of the other of the switch units connected to the same data control terminal.
Abstract translation: 数据驱动电路包括多个驱动单元，每个驱动单元包括第一，第二，第三和第四开关单元，每个开关单元包括第一和第二输入端子和输出端子; 所述输出端子是所述数据驱动电路的输出端子; 两个数据控制端子，其中一个分别连接到第一开关单元和第二开关单元的第一输入端子，另一个分别连接到第三开关单元和第四开关单元的第一输入端子; 第一开关控制端子，连接到连接到同一数据控制端子的开关单元之一的第二输入端子; 连接到连接到同一数据控制终端的另一个开关单元的第二输入端子的第二开关控制端子。
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公开(公告)号：US20170052637A1
公开(公告)日：2017-02-23
申请号：US15308385
申请日：2015-11-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jianing LU , Yuanbo ZHANG
IPC: G06F3/041
CPC classification number: G06F3/0416 , G06F3/0412 , G06F3/0418 , G06F3/044
Abstract: The present disclosure relates to a touch display panel, a method and a device for driving the touch display panel. The method is applied to the touch display panel which includes L gate lines arranged sequentially and M touch scan lines arranged sequentially, where both L and M are positive integers larger than 1. The method includes dividing a duration for which the touch display panel displays each frame of image into N control time intervals with each of the N control time intervals including a display refresh time and a touch time arranged sequentially, where N is an integer larger than 1, during the duration for which the touch display panel displays each frame of image, driving the L gate lines sequentially in N display refresh times, and driving the M touch scan lines sequentially for K times in N touch times, where K is larger than 1.
Abstract translation: 本公开涉及一种用于驱动触摸显示面板的触摸显示面板，方法和装置。 该方法应用于触摸显示面板，其包括按顺序布置的L个栅极线和顺序布置的M个触摸扫描线，其中L和M均为大于1的正整数。该方法包括将触摸显示面板显示的持续时间 在N个控制时间间隔内，每个N个控制时间间隔包括在触摸显示面板显示每帧的每个帧的持续时间期间依次布置的显示刷新时间和触摸时间，其中N是大于1的整数 图像，以N个显示刷新次序顺序驱动L个门极线，并且在N个触摸时间内依次驱动M个触摸扫描线K次，其中K大于1。
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公开(公告)号：US20160300542A1
公开(公告)日：2016-10-13
申请号：US14777587
申请日：2015-03-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yuanbo ZHANG , Seimgwoo HAN , Yunsik IM
CPC classification number: G09G3/3677 , G09G3/3266 , G09G3/3696 , G09G2300/0809 , G09G2300/0842 , G09G2310/0286 , G09G2330/06 , G11C19/28
Abstract: The present invention provides a shift register unit, a gate driving circuit and a display device, which belongs to the field of display technology. The shift register unit of the present invention comprises: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module.
Abstract translation: 本发明提供属于显示技术领域的移位寄存器单元，栅极驱动电路和显示器件。 本发明的移位寄存器单元包括：输入模块，上拉模块，下拉控制模块，下拉模块，复位模块和放电模块。
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9.发明申请公开(公告)号：US20160049126A1
公开(公告)日：2016-02-18
申请号：US14436932
申请日：2014-07-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yuanbo ZHANG , Jiayang ZHAO , Seung Woo HAN , Xing YAO , Haifeng JIN
CPC classification number: G09G3/3648 , G06F3/0416 , G09G3/36 , G09G3/3674 , G09G3/3696 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G11C19/00 , G11C19/28 , G11C19/287
Abstract: The present disclosure provides a shift register unit, a gate electrode drive circuit and a display apparatus, which relates to a technical field of display. The shift register unit includes an input reset module, a pull up module, a control module and a pull down module. By inputting a high level into the second signal input end of the input reset module in the touch scan to maintain the level at the pull up control node, the electrical leak effects at the pull up control node may be avoided efficiently. In this way, the defects of insufficient charging rate of the row pixels may be avoided and the dark lines or bad bright lines may be suppressed.
Abstract translation: 本公开提供了一种与显示技术领域有关的移位寄存器单元，栅电极驱动电路和显示装置。 移位寄存器单元包括输入复位模块，上拉模块，控制模块和下拉模块。 通过在触摸扫描中将高电平输入到输入复位模块的第二信号输入端以维持上拉控制节点处的电平，可以有效地避免上拉控制节点处的电泄漏效应。 以这种方式，可以避免行像素充电速率不足的缺陷，并且可以抑制暗线或不良亮线。
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公开(公告)号：US20190228830A1
公开(公告)日：2019-07-25
申请号：US16191746
申请日：2018-11-15
Inventor： Zhuo XU , Yuanbo ZHANG , Yajie BAI , Heecheol KIM , Peng LIANG , Hailong WU , Yi DAN
Abstract: The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.
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