公开(公告)号：US20180331131A1

公开(公告)日：2018-11-15

申请号：US15328155

申请日：2016-05-09

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Zijin LIN ,  Haisheng ZHAO ,  Xiaoguang PEI ,  Zhilong PENG ,  Dongjiang SUN

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L27/1288 ,  H01L27/1262 ,  H01L29/66742 ,  H01L29/786

摘要： A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.

公开(公告)号：US20170373099A1

公开(公告)日：2017-12-28

申请号：US15537209

申请日：2016-08-04

申请人： BOE Technology Group Co., Ltd. ,  Beijing BOE Optoelectronics Technology Co., Ltd.

发明人： Zijin LIN ,  Haisheng ZHAO ,  Zhilong PENG ,  Dongjiang SUN

IPC分类号： H01L27/12 ,  G02F1/1343 ,  G02F1/1362

CPC分类号： H01L27/1262 ,  G02F1/1343 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/123 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/78636

摘要： Disclosed are an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a gate insulating layer, an active layer, source-drain electrodes, a first conductive layer and an isolation insulating layer), the source-drain electrodes are in contact with the active layer, the gate insulating layer is located on a surface of the active layer, the isolation insulating layer) is located on another surface of the active layer, and the isolation insulating layer at least includes a first hollow structure in a contacting region of the active layer and the source-drain electrodes; the isolation insulating layer is configured to isolate residue of the active layer located outside a region where the first hollow structure is located from contacting the first conductive layer.

公开(公告)号：US20180026057A1

公开(公告)日：2018-01-25

申请号：US15647518

申请日：2017-07-12

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Lei ZHANG ,  Jiapeng LI ,  Jing ZHANG ,  Lei CHEN ,  Dongjiang SUN

IPC分类号： H01L27/142 ,  H01L27/12

CPC分类号： H01L27/142 ,  H01L27/1288

摘要： An array substrate includes a gate line, a common electrode line, a common electrode and a pixel electrode arranged on a base substrate. The common electrode is electrically connected to the common electrode line through a common electrode via-hole, and the common electrode includes a hollowed-out portion and a reserved portion at a region corresponding to the common electrode via-hole. The reserved portion is arranged between the gate line adjacent to the common electrode line and the pixel electrode adjacent to the common electrode line, and electrically connected to the common electrode line through the common electrode via-hole. The reserved portion does not overlap the gate line or the pixel electrode. The hollowed-out portion is at least arranged at a side of the reserved portion adjacent to the gate line and/or pixel electrode and between the reserved portion and the gate line and/or the pixel electrode.