公开(公告)号：US20200241369A1

公开(公告)日：2020-07-30

申请号：US15769640

申请日：2017-08-07

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Duolong DING ,  Huafeng LIU ,  Shengwei ZHAO ,  Chaochao SUN ,  Chao WANG ,  Jingping LV ,  Meng YANG ,  Lei YANG ,  Chongliang HU ,  Lin XIE ,  Bule SHUN ,  Shimin SUN

IPC分类号： G02F1/1362

摘要： A pixel structure and a manufacturing method thereof, an array substrate and a display device are provided. The pixel structure includes: a signal line; a common electrode line an extension direction of which is same as an extension direction of the signal line; a transistor including a semiconductor layer which includes a source region and a drain region; a first storage electrode which is insulated from the common electrode line and is connected with the drain region of the semiconductor layer; and a second storage electrode which is connected with the common electrode line and is insulated from the first storage electrode. In the pixel structure, portions, between the signal line and the common electrode line, of the first storage electrode and the second storage electrode includes overlap with each other to form a first storage capacitance.

公开(公告)号：US20170205953A1

公开(公告)日：2017-07-20

申请号：US15233408

申请日：2016-08-10

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

发明人： Chaochao SUN ,  Huafeng LIU ,  Shengwei ZHAO ,  Kai ZHANG ,  Lei YANG ,  Lulu YE ,  Jingping LV ,  Chao WANG ,  Chongliang HU ,  Meng YANG ,  Duolong DING ,  Bule SHUN ,  Lin XIE ,  Yao LI ,  Shimin SUN

IPC分类号： G06F3/041 ,  G02F1/1362 ,  G09G3/36 ,  H01L27/12 ,  G06F3/044

摘要： The present disclosure provides an array substrate, its driving method and manufacturing method, and a display device. The array substrate includes a transistor layer arranged on a base, and a first transparent conductive layer, a first insulation layer, a second transparent conductive layer, a second insulation layer and a third transparent conductive layer sequentially arranged on the transistor layer. The first transparent conductive layer covers the transistor layer at a display area, the second transparent conductive layer includes a pattern of touch electrodes, and the third transparent conductive layer includes a pattern of pixel electrodes. Within any pixel area of the display area, the pixel electrode is connected to a pixel electrode connection end of the transistor layer through a via-hole in the first insulation layer and the second insulation layer, and the first transparent conductive layer is provided with an opening at a position corresponding to the via-hole.