公开(公告)号：US20190027079A1

公开(公告)日：2019-01-24

申请号：US15577402

申请日：2017-05-03

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Guangliang SHANG ,  Xing YAO ,  Mingfu HAN ,  Seung-Woo HAN ,  Yun-Sik IM ,  Jing LV ,  Yinglong HUANG ,  Jung-Mok JUN ,  Xue DONG ,  Haoliang ZHENG ,  Lijun YUAN ,  Zhichong WANG ,  Ji Ha KIM

IPC分类号： G09G3/20 ,  G11C19/28

摘要： A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

公开(公告)号：US20180261177A1

公开(公告)日：2018-09-13

申请号：US15796463

申请日：2017-10-27

申请人： BOE Technology Group Co., Ltd.

发明人： Mingfu HAN ,  Xing YAO ,  Guangliang SHANG ,  Haoliang ZHENG ,  Seung-Woo HAN ,  Jiha KIM ,  Lijun YUAN ,  Zhichong WANG

IPC分类号： G09G3/36 ,  G06F3/041

CPC分类号： G09G3/3677 ,  G06F3/0412 ,  G06F3/0416 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2340/0407 ,  G11C19/28

摘要： The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US20180293956A1

公开(公告)日：2018-10-11

申请号：US15840757

申请日：2017-12-13

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Xing YAO ,  Seung-Woo HAN ,  Guangliang SHANG ,  Mingfu HAN ,  Haoliang ZHENG ,  Yun-Sik IM

IPC分类号： G09G5/00 ,  G11C19/18 ,  G11C19/28

摘要： The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a plurality of shift register units, a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. The plurality of gate lines crossing the plurality of data lines defines a plurality of pixel regions. Each of the pixel regions is divided into a driving zone and a pixel unit zone. A plurality of the driving zones in a same column constitute at least one unit region and each of the shift register units is disposed in one of the unit regions to provide scanning signals to the gate line connected thereto.