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    Timing recovery using the pilot signal in high definition TV
    2.
    发明申请
    Timing recovery using the pilot signal in high definition TV 有权
    使用高分辨率电视中的导频信号进行定时恢复

    公开(公告)号：US20020136329A1

    公开(公告)日：2002-09-26

    申请号：US10150186

    申请日：2002-05-16

    Applicant: Broadcom Corporation

    Inventor： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

    IPC: H04L027/14

    CPC classification number: H04N5/21 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/455 ,  H04N5/46 ,  H04N11/002

    Abstract: Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fcnullfs/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fs is correct, and will be shifted in one direction or the other if the sampling frequency fs is too high or too low.

    Abstract translation: 公开了适用于双模QAM / VSB接收机系统的改进的载波恢复和符号定时系统和方法。 载波和符号定时采集和跟踪环路被相位/频率锁定到在给定频率下在输入VSB频谱中提供的插入导频信号。 输入频谱以基带为中心，并且通过等效滤波器提取导频，该等效滤波器用作具有以导频频率为中心的通带的带通滤波器。 由于给出了导频信号的频率，所以在频域中对于任何采样频率的位置是确定性的。 提供接收机的采样频率，使得该关系被表示为fc = fs / 4。 当通过锁相环路进行跟踪时，如果采样频率fs正确，则导频信号将出现在频谱中的正确位置，并且如果采样频率fs太高或太低，则导频信号将在一个方向或另一个方向上移位 。

    Digital IF demodulator with carrier recovery
    3.
    发明申请
    Digital IF demodulator with carrier recovery 失效
    带载波恢复的数字IF解调器

    公开(公告)号：US20030197810A1

    公开(公告)日：2003-10-23

    申请号：US10448062

    申请日：2003-05-30

    Applicant: Broadcom Corporation

    Inventor： Steven T. Jaffe

    IPC: H04N005/455

    CPC classification number: H04N21/426 ,  H03D7/16 ,  H03J3/18 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/455 ,  H04N7/035 ,  H04N21/4263 ,  H04N2005/91364

    Abstract: A digital IF demodulator receives and demodulates an analog IF input signal to produce a digital audio signal and a digital video signal. The digital IF demodulator includes an A/D converter, a first digital complex mixer, a second digital complex mixer, and various digital filters. The first digital complex mixer receives the output of the A/D converter and down-converts the output of the A/D converter to baseband. Additionally, the picture carrier is recovered from the output of the first digital complex mixer, and fed back to a direct digital synthesizer to control the tuning accuracy of the first digital complex mixer. More specifically, a feedback loop is formed to so that the picture carrier is down-converted to DC so as to control the tuning accuracy of the first digital complex mixer. The complex output of the first complex mixer is further processed using Nyquist filtering and other filtering to recover the digital video signal. The digital audio signal is recovered by further processing the output of the first digital complex mixer. With the picture carrier located at DC, the audio signal is shifted off DC by approximately 4.5 Mhz. A second complex mixer down-converts the output of the first digital complex mixer so that the audio signal at 4.5 MHz is down-converted to baseband. After filtering and demodulation, the digital audio signal is recovered.

    Abstract translation: 数字IF解调器接收并解调模拟IF输入信号以产生数字音频信号和数字视频信号。 数字IF解调器包括A / D转换器，第一数字复合混频器，第二数字复合混频器和各种数字滤波器。 第一个数字混合混频器接收A / D转换器的输出，并将A / D转换器的输出下变频为基带。 此外，图像载体从第一数字复合混频器的输出恢复，并被反馈到直接数字合成器以控制第一数字复合混频器的调谐精度。 更具体地，形成反馈环路，使得图像载波被下变频为DC，以便控制第一数字复合混频器的调谐精度。 使用奈奎斯特滤波和其他滤波进一步处理第一复合混频器的复合输出以恢复数字视频信号。 通过进一步处理第一数字复合混合器的输出来恢复数字音频信号。 在图像载体位于DC处，音频信号从DC偏离大约4.5Mhz。 第二复合混频器将第一数字复合混频器的输出降频转换，使得4.5MHz的音频信号被下变频到基带。 滤波和解调后，数字音频信号被恢复。

    Digital IF demodulator
    5.
    发明申请
    Digital IF demodulator 有权
    数字中频解调器

    公开(公告)号：US20040223086A1

    公开(公告)日：2004-11-11

    申请号：US10776991

    申请日：2004-02-12

    Applicant: Broadcom Corporation

    Inventor： Steven T. Jaffe

    IPC: H04N005/455

    CPC classification number: H04N5/455 ,  H03D7/16 ,  H03J3/18 ,  H04N5/44 ,  H04N5/4401 ,  H04N7/035 ,  H04N21/426 ,  H04N21/4263 ,  H04N2005/91364

    Abstract: A digital IF demodulator includes an analog-to-digital (A/D) converter that receives an analog IF signal and converts it to a digital IF signal. A parallel multiplier then down-converts the digital IF signal to a baseband signal having a video component and an audio component. The frequency down-conversion uses a parallel multiplier driven by an outer feedback loop that corrects gross frequency errors in said digital IF signal. The digital IF demodulator also includes a video recovery circuit that selects the video component from the baseband signal and further down-converts the baseband signal to a video baseband using a video complex mixer driven by an inner feedback loop that corrects fast phase perturbations in the video recovery circuit. Finally, the digital IF demodulator includes an audio recovery circuit that (i) receives said baseband signal from the parallel multiplier, and (ii) down-converts the audio component to an audio baseband signal using an audio complex mixer.

    Abstract translation: 数字IF解调器包括模拟数字（A / D）转换器，其接收模拟IF信号并将其转换为数字IF信号。 然后并行乘法器将数字IF信号下变频为具有视频分量和音频分量的基带信号。 降频转换使用由外部反馈环路驱动的并行乘法器，其校正所述数字IF信号中的总频率误差。 数字IF解调器还包括视频恢复电路，其从基带信号中选择视频分量，并且使用由内部反馈环路驱动的视频复合混合器进一步将基带信号下变频到视频基带，该内部反馈环路校正视频中的快速相位扰动 恢复电路。 最后，数字IF解调器包括：（i）从并行乘法器接收所述基带信号的音频恢复电路，以及（ii）使用音频复合混频器将音频分量下变频为音频基带信号。

    Equalization and decision-directed loops with trellis demodulation in high definition TV
    7.
    发明申请
    Equalization and decision-directed loops with trellis demodulation in high definition TV 有权
    均衡和决策导向循环与高分辨率电视网格解调

    公开(公告)号：US20040258184A1

    公开(公告)日：2004-12-23

    申请号：US10895879

    申请日：2004-07-21

    Applicant: Broadcom Corporation

    Inventor： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

    IPC: H04L027/06

    CPC classification number: H04L27/3827 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

    Abstract: Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

    Abstract translation: 公开了改进的决策反馈均衡器和适用于与双模式QAM / VSB接收机系统相关联的决策定向定时恢复系统和方法。 网格解码器与网格编码的8-VSB调制信号上的判决反馈均衡器电路结合操作。 网格解码器包括基于最大似然序列路径输出最大似然判定以及多个中间决策的4状态追迹存储器电路。 沿序列的任何数量的决定可以作为输入信号提供给定时恢复系统循环，其中沿着根据其通过网格解码器的延迟选择的序列的特定决定。 可变延迟电路耦合到定时恢复系统回路的另一个输入，以确保两个输入信号具有相同的时间戳。 最终决策从网格解码器输出到DF​​E，以提高DFE在低SNR环境下的运行能力。 还产生判决序列估计误差信号并用于驱动均衡器的DFE和FFE部分的抽头更新。

    Decision feedback equalizer and precoder ramping circuit
    8.
    发明申请
    Decision feedback equalizer and precoder ramping circuit 有权
    决策反馈均衡器和预编码器斜坡电路

    公开(公告)号：US20040252755A1

    公开(公告)日：2004-12-16

    申请号：US10848907

    申请日：2004-05-19

    Applicant: BROADCOM CORPORATION

    Inventor： Steven T. Jaffe ,  Robindra Joshi ,  David Jones ,  Thuji Simon Lin

    IPC: H03K005/159 ,  H04B001/10

    CPC classification number: H04L25/4975 ,  H03H21/0012 ,  H04L25/03343 ,  H04L25/03993 ,  H04L2025/0349 ,  H04L2025/03808

    Abstract: A feedforward filter has a plurality of feedforward filter taps, including a feedforward filter reference tap. The reference tap of the feedforward filter is positioned proximate a center position of the feedforward filter. A ramping circuit assembly has an input port configured to receive at least one decision feedback filter tap coefficient from a decision feedback filter. A coefficient ramping circuit is configured to provide a ramped output for at least one of the decision feedback filter tap coefficients. The ramped output is varied over time from a first value to a second value. The second value is dependent upon the value of a decision feedback filter tap coefficient. An output port of the ramping circuit assembly is configured to communicate information representative of the ramped output(s) to a precoder.

    Abstract translation: 前馈滤波器具有多个前馈滤波器抽头，包括前馈滤波器参考抽头。 前馈滤波器的参考抽头位于前馈滤波器的中心位置附近。 斜坡电路组件具有被配置为从判决反馈滤波器接收至少一个判决反馈滤波器抽头系数的输入端口。 系数斜坡电路被配置为为决策反馈滤波器抽头系数中的至少一个提供斜坡输出。 斜坡输出随时间从第一个值变化到第二个值。 第二个值取决于决策反馈滤波器抽头系数的值。 斜坡电路组件的输出端口被配置为将表示斜坡输出的信息传送到预编码器。

    INTERSPERSED TRAINING FOR TURBO CODED MODULATION
    9.
    发明申请
    INTERSPERSED TRAINING FOR TURBO CODED MODULATION 失效
    用于涡轮编码调制的交互式训练

    公开(公告)号：US20040090352A1

    公开(公告)日：2004-05-13

    申请号：US10703286

    申请日：2003-11-07

    Applicant: BROADCOM CORPORATION

    Inventor： Steven T. Jaffe ,  Kelly B. Cameron

    IPC: H03M007/00

    CPC classification number: H04L1/0057 ,  H03M13/1515 ,  H03M13/2966 ,  H04B7/18589 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0071 ,  H04L1/0083 ,  H04L25/0226 ,  H04L27/0014 ,  H04L2027/0028 ,  H04L2027/0034 ,  H04L2027/0036

    Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset. Phase lock to a signal may achieved after determining carrier offset in receivers by con-elating successive symbols in successive headers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

    Abstract translation: 具有组合Reed-Solomon编码器和Turbo-Code编码器数据帧配置的通信系统可以被改变以适应已知值的嵌入式子标记，以数据顺序嵌入以辅助接收机系统中的同步，通过提供串 已知符号。 已知符号串可以与出现在数据帧开始处的训练头中的符号相同。 帧参数可以针对个体用户定制，并且可以由与接收机有关的信息（例如接收机的比特错误率）来控制。 额外的头可以散布在数据内，以帮助接收机同步。 为了确定载波偏移，可以由接收机通过在标题训练序列中的连续首标符号之间具有表示相位偏移的符号串来快速获取数据帧。 在确定接收机中的载波偏移之后，可以通过连续的连续标头中的连续符号来实现对信号的相位锁定。 要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Timing recovery using the pilot signal in high definition TV
    10.
    发明申请
    Timing recovery using the pilot signal in high definition TV 有权
    使用高分辨率电视中的导频信号进行定时恢复

    公开(公告)号：US20040258180A1

    公开(公告)日：2004-12-23

    申请号：US10895579

    申请日：2004-07-21

    Applicant: Broadcom Corporation

    Inventor： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

    IPC: H04L027/14

    CPC classification number: H04N5/21 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/455 ,  H04N5/46 ,  H04N11/002

    Abstract: Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fcnullfS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

    Abstract translation: 公开了适用于双模QAM / VSB接收机系统的改进的载波恢复和符号定时系统和方法。 载波和符号定时采集和跟踪环路被相位/频率锁定到在给定频率下在输入VSB频谱中提供的插入导频信号。 输入频谱以基带为中心，并且通过等效滤波器提取导频，该等效滤波器用作具有以导频频率为中心的通带的带通滤波器。 由于给出了导频信号的频率，所以在频域中对于任何采样频率的位置是确定性的。 提供接收机的采样频率，使得该关系被表示为fc = fS / 4。 当通过锁相环路进行跟踪时，如果采样频率fS正确，则导频信号将出现在频谱中的正确位置，并且如果采样频率fS太高或太低，则导频信号将在一个方向或另一个方向上移位 。

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