公开(公告)号：US3582683A

公开(公告)日：1971-06-01

申请号：US3582683D

申请日：1968-08-09

Applicant: BUNKER RAMO

Inventor： PODRAZA GEORGE V

IPC: H03K19/0944 ,  H03K19/096 ,  H03K17/00

CPC classification number: H03K19/096 ,  H03K19/09441

Abstract: Inverting switching and logic function circuits for digital equipment are provided in networks with an option for phase clocking by including first and second insulated-gate (MOS), field-effect transistors having their source connected to the functional circuit output terminal. The drain and gate of the first transistor are adapted to be connected to a clock source for clocked mode of operation and to circuit ground for nonclocked mode of operation. The gate of the first transistor is also so connected to the functional circuit as to provide circuit ground thereto permanently for a nonclocked mode of operation, and to provide clock pulses thereto for a clocked mode of operation, such that the functional circuit is biased off in reference to circuit ground potential during clock pulses to charge stray capacitance at the functional circuit output terminal, but enabled as a function of one or more input signals between clock pulses to discharge the stray capacitance. The second transistor connected to the output terminal is adapted to be biased for conduction as a load transistor when the first transistor is connected to circuit ground such that the stray capacitance is then charged through the load transistor and discharged through the circuit as a function of one or more input signals in a nonclocked mode of operation for the network.

公开(公告)号：US3518635A

公开(公告)日：1970-06-30

申请号：US3518635D

申请日：1967-08-22

Applicant: BUNKER RAMO

Inventor： COLE ROBERT H ,  NISSIM SAMUEL ,  PODRAZA GEORGE V ,  FEUER ROBERT

IPC: G11C11/402 ,  H03K3/356 ,  G11C11/40 ,  H03K3/286

CPC classification number: H03K3/35606 ,  G11C11/4023

公开(公告)号：US3603816A

公开(公告)日：1971-09-07

申请号：US3603816D

申请日：1968-08-09

Applicant: BUNKER RAMO

Inventor： PODRAZA GEORGE V

IPC: H03K3/356 ,  H03K19/017 ,  H03K19/40 ,  H03K19/00

CPC classification number: H03K3/356026 ,  H03K19/01742

Abstract: Apparatus is provided in digital data equipment for transferring a binary signal to a flip-flop, and deriving therefrom a buffered output signal representing the state into which said flip-flop is being switched by anticipation means coupling the input terminal of the flip-flop to a buffer amplifier driven by the flip-flop. A multibranch, multistage selector tree is employed to selectively couple one of a number of binary signals to the flip-flop. The anticipation means and selector tree overcome and minimize the limitations in switching speeds inherent in such apparatus implemented with insulated-gate, field-effect transistors in an integrated circuit. Switching speed of the flip-flop is increased by the combination of (1) a push-pull arrangement such that when a binary signal is applied to one side the complement of the binary signal is applied to the other side, and (2) an anticipation circuit temporarily shunting current around a load resistor in series with a given one of two cross-coupled active elements.