公开(公告)号：US4104546A

公开(公告)日：1978-08-01

申请号：US769431

申请日：1977-02-17

申请人： Hartmut Seiler

发明人： Hartmut Seiler

IPC分类号： H01L27/04 ,  G01R19/165 ,  H01L21/822 ,  H03K17/30 ,  H03K19/0175 ,  H03K5/20 ,  H03K19/40

CPC分类号： G01R19/16576 ,  H03K17/30 ,  H03K19/017581

摘要： To reliably ensure response of integrated circuits having threshold inputs, while rejecting interference and noise pulses, the input stage is formed with a plurality of resistors which can be selectively vaporized or burned off to match the input response of the threshold circuit to any input operating voltage without requiring the use of discrete, replaceable input resistors. Preferably, the input voltages are conducted to voltage dividers which have resistors which can be selectively removed by evaporation or burning off. The circuit can also have inverters bridged by a vaporizable shunt to respond to voltages of selected polarity or provide an output of selected polarity.

摘要翻译： 为了可靠地确保具有阈值输入的集成电路的响应，在抑制干扰和噪声脉冲的同时，输入级形成有多个电阻器，其可以选择性地蒸发或烧掉以将阈值电路的输入响应与任何输入工作电压 而不需要使用离散的，可更换的输入电阻。 优选地，输入电压被传导到具有电阻器的分压器，电阻器可以通过蒸发或燃烧而被选择性地去除。 电路还可以具有由可汽化分流器桥接的逆变器以响应所选极性的电压或提供所选极性的输出。

公开(公告)号：US4065678A

公开(公告)日：1977-12-27

申请号：US702366

申请日：1976-07-02

申请人： Edmund Arthur Reese ,  Charles Shelley Meyer ,  George S. Leach, Jr.

发明人： Edmund Arthur Reese ,  Charles Shelley Meyer ,  George S. Leach, Jr.

IPC分类号： H03K5/02 ,  H03K5/08 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K19/017 ,  H03K19/01714 ,  H03K19/018507 ,  H03K5/023 ,  H03K5/082

摘要： A clamped push-pull driver circuit suitable for driving high capacitive loads includes a bootstrap MOS inverter circuit driving an MOS push-pull driver circuit. A regulator circuit including a plurality of diode-connected MOSFETs is coupled between the output of the MOS bootstrap inverter and a ground conductor. A MOSFET (the feedback device) having its gate electrode coupled to the output of the MOS push-pull circuit is connected in series with the diode-connected MOSFETs. Rapid rise time and short delay are achieved at the output of the clamped push-pull driver circuit, since the regulator circuit does not begin to conduct current (i.e., does not start the clamping action) until the output voltage of the push-pull driver circuit has exceeded two thresholds. Thus a large drive capability is provided to initiate the rising action of the output signal and clamping only begins to occur after the output is already rising towards a higher virtual final level than that which clamping will allow. This delayed clamping action is controlled by the feedback MOSFET which is positioned between two of the diode-connected MOSFETs so that the feedback MOSFET is not turned on until the desired voltage is achieved at the output of the MOS push-pull driver circuit. The output of the MOS push-pull driver will continue to rise until it reaches a level which is one threshold below that set by the plurality of diode-connected MOSFETs. The final voltage, at the end of the rise time, at the output of the MOS push-pull driver circuit tracks with the MOS threshold voltage.

摘要翻译： 适用于驱动高容性负载的钳位推挽驱动电路包括驱动MOS推挽驱动电路的自举MOS反相器电路。 包括多个二极管连接的MOSFET的调节器电路耦合在MOS自举逆变器的输出端和接地导体之间。 将其栅电极耦合到MOS推挽电路的输出的MOSFET（反馈装置）与二极管连接的MOSFET串联连接。 由于调节器电路在推挽驱动器的输出电压之前不开始导通电流（即不开始钳位动作），所以在钳位推挽驱动电路的输出端实现快速上升时间和短时间延迟 电路已超过两个阈值。 因此，提供了大的驱动能力以启动输出信号的上升动作，并且只有在输出已经朝向比夹紧允许的更高的虚拟最终级别上升之后，才开始发生钳位。 这种延迟钳位动作由位于两个二极管连接的MOSFET之间的反馈MOSFET控制，使得反馈MOSFET在MOS推挽驱动电路的输出端实现所需的电压之前不导通。 MOS推挽驱动器的输出将继续上升，直到其达到低于由多个二极管连接的MOSFET设定的阈值以下的阈值的电平。 在MOS推挽驱动电路的输出端，上升时间结束时的最终电压跟踪MOS阈值电压。

公开(公告)号：US4037115A

公开(公告)日：1977-07-19

申请号：US699950

申请日：1976-06-25

申请人： Charles Meng-Yuan Lee

发明人： Charles Meng-Yuan Lee

IPC分类号： H03K19/088 ,  H03K19/40 ,  H03K5/08

CPC分类号： H03K19/088

摘要： A transistor-transistor logic gate is described which uses a number of bipolar switching transistors clamped in several different ways. In particular to better adapt a bipolar switching transistor to high frequency, high temperature operation, the collectors of the various switching transistors are clamped in a variety of novel ways, each to achieve a collector voltage higher than that normally achieved by the conventional Schottky diode clamp connected between the base and collector.

摘要翻译： 描述了晶体管晶体管逻辑门，其使用以若干不同方式钳位的多个双极性开关晶体管。 特别是为了更好地将双极开关晶体管适应于高频，高温操作，各种开关晶体管的集电极以各种新颖的方式被钳位，每种都采用高于通常由常规肖特基二极管钳位实现的集电极电压 连接在基座和收集器之间。

公开(公告)号：US4000411A

公开(公告)日：1976-12-28

申请号：US570825

申请日：1975-04-23

申请人： Kenji Sano ,  Hiroaki Arai

发明人： Kenji Sano ,  Hiroaki Arai

IPC分类号： H03F3/345 ,  H03F3/34 ,  H03K17/30 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K19/09441 ,  H03K19/09443

摘要： A MOS logic circuit includes a source follower circuit arrangement consisting of a driver MOS element, in addition to a transfer MOS element, an inverter MOS element and a load MOS element. The transfer MOS element receives input signals at its source and produces output signals at its drain, the output signals being applied to the gate of the driver MOS element contained within the source follower circuit arrangement. The resulting output signals developed at the source of the driver MOS element are supplied to the inverter MOS element. This permits the slice or boundary level between the logical 1 and 0 to be higher than the given threshold level of the MOS elements.

摘要翻译： MOS逻辑电路包括除了传输MOS元件之外的驱动器MOS元件，反相器MOS元件和负载MOS元件的源极跟随器电路装置。 传输MOS元件在其源极处接收输入信号并在其漏极处产生输出信号，输出信号被施加到源极跟随器电路布置中包含的驱动器MOS元件的栅极。 在驱动器MOS元件的源极处产生的产生的输出信号被提供给反相器MOS元件。 这允许逻辑1和0之间的片或边界电平高于MOS元件的给定阈值电平。

公开(公告)号：US3986044A

公开(公告)日：1976-10-12

申请号：US612996

申请日：1975-09-12

申请人： Paul Dale Madland ,  M. Clair Webb

发明人： Paul Dale Madland ,  M. Clair Webb

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K19/01728 ,  H03K19/01855

摘要： A voltage level sustaining circuit for an IGFET driver circuit having an output node includes a first IGFET coupled between a voltage supply conductor and an output node of a driver circuit. The gate of the first IGFET is coupled to a source of a second IGFET having its gate and drain connected to the voltage supply conductor. A boosting capacitor is connected between the gate of the first IGFET and a conductor to which a refresh pulse is applied. The refresh pulse need be applied only often enough and be of sufficient magnitude to turn on the first IGFET sufficiently hard that the output node is held at the voltage of the voltage supply conductor.

摘要翻译： 具有输出节点的IGFET驱动器电路的电压电平维持电路包括耦合在电压供应导体和驱动器电路的输出节点之间的第一IGFET。 第一IGFET的栅极耦合到第二IGFET的源极，其栅极和漏极连接到电压供应导体。 升压电容器连接在第一IGFET的栅极和施加刷新脉冲的导体之间。 刷新脉冲仅需要经常被施加并且具有足够的量级以使得第一IGFET足够坚硬以使输出节点保持在电压供应导体的电压。

公开(公告)号：US3980898A

公开(公告)日：1976-09-14

申请号：US557597

申请日：1975-03-12

申请人： Ury Priel

发明人： Ury Priel

IPC分类号： H03K19/018 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/082 ,  H03K19/20 ,  H03K19/08 ,  H03K5/08 ,  H03K19/38 ,  H03K19/40

CPC分类号： H03K19/0021 ,  H03K19/017581 ,  H03K19/0826

摘要： A novel sense amplifier circuit providing conversion of MOS input signals to TTL output signals with tri-state logic output at the output data bus, the input circuit of the sense amplifier providing current sensing and programmable input thresholds for economical construction and enhanced speed of operation of the sense amplifier. A novel tri-state operation is provided for the input section of the sense amplifier to provide either a clamped voltage at the input data bus line during MOS to TTL communication or a floating input when it is desired that MOS devices on the input data bus are to communicate.

摘要翻译： 一种新颖的读出放大器电路，提供MOS输入信号到输出数据总线上具有三态逻辑输出的TTL输出信号的转换，读出放大器的输入电路提供电流检测和可编程输入阈值，用于经济建设和提高运行速度 读出放大器。 提供了一种新颖的三态操作，用于读出放大器的输入部分，以便在MOS到TTL通信期间在输入数据总线处提供钳位电压，或者当希望输入数据总线上的MOS器件为 沟通。

公开(公告)号：US3973139A

公开(公告)日：1976-08-03

申请号：US363255

申请日：1973-05-23

申请人： Andrew Gordon Francis Dingwall

发明人： Andrew Gordon Francis Dingwall

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K23/44 ,  H03K23/02 ,  H03K17/60 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K23/44 ,  H03K3/037 ,  H03K3/356104

摘要： A counter stage comprising a static inverter and first and second dynamic inverting means. Each inverting means includes an input, an output, and means for selectively rendering the inverting means operative. The output of the first inverting means is applied to the input of the static inverter, the output of the static inverter is applied to the input of the second inverting means and the output of the second inverting means is fed back to the input of the first inverting means. When one inverting means is rendered operative, the other inverting means is rendered inoperative.

摘要翻译： 一个包括静态逆变器和第一和第二动态反转装置的计数器级。 每个反相装置包括一个输入端，一个输出端和用于有选择地使该反相装置工作的装置。 第一反相装置的输出被施加到静态逆变器的输入端，静态逆变器的输出被施加到第二反相装置的输入，第二反相装置的输出反馈到第一反相装置的输入端 反转装置。 当一个反转装置可操作时，另一个反转装置变得不可操作。

公开(公告)号：US3935474A

公开(公告)日：1976-01-27

申请号：US450826

申请日：1974-03-13

申请人： James A. Komarek

发明人： James A. Komarek

IPC分类号： G11C19/28 ,  H03K3/356 ,  H03K19/096 ,  H03K19/08 ,  H03K19/36 ,  H03K19/40

CPC分类号： H03K19/096

摘要： In a logic cell, a plurality of gates are serially connected and responsive to signals on a plurality of conductors to perform a particular logic function. The gates are responsive to subsystem clock signals which control the operation of the gates to delay the output of the logic cell. The cell includes at least one ratioless gate, and at least one ratioed gate. The ratioless gates provide high speed and reduced size, while the ratioed gates provide low noise characteristics. In combination, the ratioed gates, which provide strong output signals, make excellent drivers for the ratioless gates which are particularly adapted to accommodate complex logic networks.

摘要翻译： 在逻辑单元中，多个栅极串联并且响应于多个导体上的信号以执行特定的逻辑功能。 门响应于子系统时钟信号，其控制门的操作以延迟逻辑单元的输出。 电池包括至少一个无大门和至少一个比例的门。 无门门提供高速度和减小的尺寸，而比例门提供低噪声特性。 结合起来，提供强输出信号的比例门对于非常适合于适应复杂逻辑网络的无限大门而言是出色的驱动器。

公开(公告)号：US3790817A

公开(公告)日：1974-02-05

申请号：US3790817D

申请日：1972-02-14

申请人： NAT SEMICONDUCTOR CORP

发明人： DOBKIN R

IPC分类号： H03K19/013 ,  H03K19/40 ,  H03K19/08

CPC分类号： H03K19/013

摘要： A low power TTL gating circuit wherein PNP transistors have been used in place of the usual current source resistors and Schottkyclamped NPN have been used in place of the usual gold doped NPN gating elements to obtain a faster operating circuit which requires less chip area than similar prior art circuits.

摘要翻译： 已经使用其中使用PNP晶体管代替通常的电流源电阻器和肖特基钳位NPN的低功率TTL门控电路来代替通常的金掺杂NPN选通元件，以获得更快的操作电路，其需要较少的芯片面积 类似的现有技术电路。

公开(公告)号：US3766406A

公开(公告)日：1973-10-16

申请号：US3766406D

申请日：1971-12-06

申请人： COGAR CORP

发明人： BRYANT R ,  TU G

IPC分类号： H03K19/018 ,  H03K19/08 ,  H03K19/40

CPC分类号： H03K19/01812

摘要： An ECL-to-TTL converter having an ECL input stage for deriving a signal to drive a TTL output stage. The TTL output stage includes a pair of transistors arranged in a push-pull configuration for maximum speed of operation.

摘要翻译： 具有用于导出信号以驱动TTL输出级的ECL输入级的ECL至TTL转换器。 TTL输出级包括以推挽配置布置的一对晶体管，以实现最大的操作速度。