Digital data communication multiple line control
    2.
    发明授权
    Digital data communication multiple line control 失效
    数字数据通信多线控制

    公开(公告)号:US3618037A

    公开(公告)日:1971-11-02

    申请号:US3618037D

    申请日:1969-09-19

    Applicant: BURROUGHS CORP

    CPC classification number: G06F13/22 G06F13/385

    Abstract: There is described a control unit for buffering a plurality of digital data communication lines with a data processor on a timeshared basis, where each communication line may be operating with a different line discipline. All buffering functions for each communication line are under control of a stored word. The stored control words, together with each of the associated communication line adapter terminals, are continuously scanned and logic circuitry, in response to each control word when scanned, determines the status of the communication and modifies the control word if the status has changed. Timing functions for all communication lines are derived, also on a time-shared basis, from a single real-time clock. The processor can monitor each control word during each scan to change the status of the communication operation with the associated line and to sense interrupt conditions requiring attention.

    Data processing system having an improved fetch overlap feature
    4.
    发明授权
    Data processing system having an improved fetch overlap feature 失效
    具有改进的FETCH覆盖特征的数据处理系统

    公开(公告)号:US3609700A

    公开(公告)日:1971-09-28

    申请号:US3609700D

    申请日:1970-02-24

    Applicant: BURROUGHS CORP

    CPC classification number: G06F9/3802 G06F9/3824 G06F9/3867 G06F13/161

    Abstract: An improvement in a fetch overlap feature for a data processing system results from providing multiple interfaces between the system data processor and the system memory. The memory is divided into a plurality of independent units each having its own interface. The data processor can retrieve more than one word from the memory system at the same time without incurring contention between memory access orders. The data processor is thereby enabled to begin to fetch its next instruction even if its current instruction orders the data processor to retrieve an operand.

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