Abstract:
There is described a control unit for buffering a plurality of digital data communication lines with a data processor on a timeshared basis, where each communication line may be operating with a different line discipline. All buffering functions for each communication line are under control of a stored word. The stored control words, together with each of the associated communication line adapter terminals, are continuously scanned and logic circuitry, in response to each control word when scanned, determines the status of the communication and modifies the control word if the status has changed. Timing functions for all communication lines are derived, also on a time-shared basis, from a single real-time clock. The processor can monitor each control word during each scan to change the status of the communication operation with the associated line and to sense interrupt conditions requiring attention.
Abstract:
A data communication system in which a single control logic function is tested by writing a test control word for one communication line into a time-shared control circuit register from a processor. The control word together with a test line input word generated by the processor are coupled to the control logic for one clock period to perform one step of the logic function, the result being stored in memory. The result is then interrogated in memory to determine if the result of the logic function meets the test.
Abstract:
An improvement in a fetch overlap feature for a data processing system results from providing multiple interfaces between the system data processor and the system memory. The memory is divided into a plurality of independent units each having its own interface. The data processor can retrieve more than one word from the memory system at the same time without incurring contention between memory access orders. The data processor is thereby enabled to begin to fetch its next instruction even if its current instruction orders the data processor to retrieve an operand.