Abstract:
A data processor having a memory in which stacks of information are stored. The top two words of an information stack, currently being operated on, are stored in two registers external to memory. An extension register is provided for each of the aforementioned registers to allow the handling of double length information units. The operand words stored in the registers have tag bits as a part thereof which identify the operands as single or double word length information units. Control circuitry is responsive to the tag bits for causing the words to be automatically manipulated or handled as single or double word length information units. A processing unit processes the data stored in the registers.
Abstract:
The overlay of information from the computer memory to a peripheral memory and its return to the computer memory are facilitated by a unique format for original and copy descriptors. The copy descriptors have a first field that designates either a base address or the location of its original, and a second field that designates an index. The original descriptors have a field that designates the base address. The copy descriptors are automatically generated from their originals. When a copy descriptor is retrieved, the first and second fields are added to form the absolute address if the first field is the base address. If the first field is an original descriptor location, the base address of the original descriptor and the index of the copy descriptor are added to form the absolute address. Upon overlay, the copy descriptors to be updated are sensed by comparing their base value with the base value of the array to be overlaid. They are updated by substituting the original descriptor location for the base address and the original descriptors are updated by substituting the peripheral memory address for the base address. Upon return of the overlaid information to the computer memory, only the original descriptor must be updated.