公开(公告)号：US20110140170A1

公开(公告)日：2011-06-16

申请号：US12958241

申请日：2010-12-01

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78687 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66742

Abstract: A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.

Abstract translation: 外延生长的梯度SiGe牺牲层覆盖在硅衬底上。 然后通过覆盖渐变SiGe层的外延工艺生长单晶硅层。 接着，通过外延工艺生长SiGe层作为覆盖硅层的单晶层。 成为晶体管的有源硅层的随后的硅层被外延生长，覆盖在第二硅锗层上。 外延生长的Si，SiGe和Si层一起形成层压半导体结构。 然后在单晶硅的有源区上形成MOS晶体管。 通过蚀刻工艺去除渐变的SiGe牺牲层以将层压半导体结构与衬底电隔离。

公开(公告)号：US20130168743A1

公开(公告)日：2013-07-04

申请号：US13341592

申请日：2011-12-30

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66553 ,  H01L21/28114 ,  H01L23/5226 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.

Abstract translation: 提供了一种应变增强型晶体管，其具有覆盖栅电极的应变诱导层。 栅电极在晶体管的沟道区域上具有倾斜的侧壁。

公开(公告)号：US08659059B2

公开(公告)日：2014-02-25

申请号：US13341592

申请日：2011-12-30

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L29/76

CPC classification number: H01L29/66553 ,  H01L21/28114 ,  H01L23/5226 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.

Abstract translation: 提供了一种应变增强型晶体管，其具有覆盖栅电极的应变诱导层。 栅电极在晶体管的沟道区域上具有倾斜的侧壁。

公开(公告)号：US08609508B2

公开(公告)日：2013-12-17

申请号：US12963474

申请日：2010-12-08

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L21/76 ,  H01L21/70 ,  H01L23/58

CPC classification number: H01L29/78 ,  H01L21/76232 ,  H01L21/764 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7846

Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

Abstract translation: 在与MOS晶体管相邻的半导体衬底中形成浅沟槽隔离。 浅沟槽填充有填充材料，同时执行其他处理步骤。 填充材料稍后通过蚀刻到沟槽上方的薄的阱中去除，留下沟槽中空。 然后在中空沟槽的侧壁上形成薄的应变诱导层。 然后将孔插入，留下沟槽基本上是中空的，除了沟槽侧壁上的薄应变诱导层。 应变诱导层被配置为在MOS晶体管的沟道区域上引起压缩或拉伸应变，从而增强晶体管的导电特性。

公开(公告)号：US08216904B2

公开(公告)日：2012-07-10

申请号：US12651217

申请日：2009-12-31

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L21/762 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/6659 ,  H01L29/7833

Abstract: According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer.

Abstract translation: 根据一个实施例，提供了在其中形成有至少两个晶体管区域的半导体衬底。 覆盖沟道区域是栅极电介质和位于栅极电介质上方的晶体管栅电极，并且位于沟道区域上方。 源极和漏极区域形成在沟道区域的两侧以产生晶体管结构。 为了在半导体衬底中的晶体管之间提供隔离，在衬底中形成沟槽。 然后将应变诱导层沉积在晶体管结构上并进入半导体衬底中的沟槽中。 高应力氮化物层是适合于形成应变诱导层的一种材料。

公开(公告)号：US08716752B2

公开(公告)日：2014-05-06

申请号：US12958241

申请日：2010-12-01

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78687 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66742

Abstract: A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.

Abstract translation: 外延生长的梯度SiGe牺牲层覆盖在硅衬底上。 然后通过覆盖渐变SiGe层的外延工艺生长单晶硅层。 接着，通过外延工艺生长SiGe层作为覆盖硅层的单晶层。 成为晶体管的有源硅层的随后的硅层被外延生长，覆盖在第二硅锗层上。 外延生长的Si，SiGe和Si层一起形成层压半导体结构。 然后在单晶硅的有源区上形成MOS晶体管。 通过蚀刻工艺去除渐变的SiGe牺牲层以将层压半导体结构与衬底电隔离。

公开(公告)号：US20120146152A1

公开(公告)日：2012-06-14

申请号：US12963474

申请日：2010-12-08

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/76232 ,  H01L21/764 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7846

Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

Abstract translation: 在与MOS晶体管相邻的半导体衬底中形成浅沟槽隔离。 浅沟槽填充有填充材料，同时执行其他处理步骤。 填充材料稍后通过蚀刻到沟槽上方的薄的阱中去除，留下沟槽中空。 然后在中空沟槽的侧壁上形成薄的应变诱导层。 然后将孔插入，留下沟槽基本上是中空的，除了沟槽侧壁上的薄应变诱导层。 应变诱导层被配置为在MOS晶体管的沟道区域上引起压缩或拉伸应变，从而增强晶体管的导电特性。

公开(公告)号：US20100164000A1

公开(公告)日：2010-07-01

申请号：US12651217

申请日：2009-12-31

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L27/085 ,  H01L21/336

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/6659 ,  H01L29/7833

Abstract: According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer.

Abstract translation: 根据一个实施例，提供了在其中形成有至少两个晶体管区域的半导体衬底。 覆盖沟道区域是栅极电介质和位于栅极电介质上方的晶体管栅电极，并且位于沟道区域上方。 源极和漏极区域形成在沟道区域的两侧以产生晶体管结构。 为了在半导体衬底中的晶体管之间提供隔离，在衬底中形成沟槽。 然后将应变诱导层沉积在晶体管结构上并进入半导体衬底中的沟槽中。 高应力氮化物层是适合于形成应变诱导层的一种材料。