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    Disk format for secondary storage system
    1.
    发明授权
    Disk format for secondary storage system 失效
    辅助存储系统的磁盘格式

    公开(公告)号：US4434487A

    公开(公告)日：1984-02-28

    申请号：US308771

    申请日：1981-10-05

    申请人： Barry L. Rubinson ,  Mark A. Parenti ,  Richard F. Lary ,  Edward A. Gardner

    发明人： Barry L. Rubinson ,  Mark A. Parenti ,  Richard F. Lary ,  Edward A. Gardner

    IPC分类号： G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G06F11/10

    CPC分类号： G11B20/1883 ,  G11B20/1252 ,  G11B20/1803 ,  G11B2220/20 ,  G11B2220/2508

    摘要： In a disk mass storage facility for data processing systems, a disk format which improves handling of defective segments of medium and reduces access time. The format has three layers. A first, physical layer comprises the bytes, sectors and collections of sectors, as well as error detection and correction codes. A second, logical layer is used to address the physical layer and to collect together sectors to form a multiplicity of separately addressable spaces, with each space having a distinct functional utility. At a third, functional layer the use of data fields in each space is specified. This layer governs the handling of bad blocks if required, and the use of certain format information. Handling of bad blocks is controlled by a hierarchically layered process. A portion of each disc, distributed across the medium, is reserved as spare sectors to replace defective sectors. After a bad sector is replaced, future attempts to access the bad sector are redirected (i.e., revectored) to the replacement sector. For the simplest revectoring, the bad block is replaced by a replacement block in a known location. If that cannot be done, multiple copies of the replacement block's header are stored in the bad block's data field and the copies are compared to find the replacement address. If the comparison fails, or the header cannot be read, a back-up table is available to match the available replacement addresses with the original address which was replaced. A special code is used to identify blocks wherein the medium is good but the contents of the block are logically corrupted.

    Apparatus and method for controlling digital data processing system employing multiple processors
    2.
    发明授权
    Apparatus and method for controlling digital data processing system employing multiple processors 失效
    用于控制采用多个处理器的数字数据处理系统的装置和方法

    公开(公告)号：US4543626A

    公开(公告)日：1985-09-24

    申请号：US447228

    申请日：1982-12-06

    申请人： Robert Bean ,  Edward A. Gardner ,  Michael Chow ,  Barry L. Rubinson ,  Richard F. Lary ,  Robert Blackledge

    发明人： Robert Bean ,  Edward A. Gardner ,  Michael Chow ,  Barry L. Rubinson ,  Richard F. Lary ,  Robert Blackledge

    IPC分类号： G06F9/48 ,  G06F15/16 ,  G06F15/177 ,  G06F13/00

    CPC分类号： G06F9/4881 ,  G06F15/161

    摘要： A control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each command is associated with a route comprising a sequence of route vectors, each identifying an operation to be performed to execute the command, as well as the process, or station, to execute the route vector. In response to the receipt of a command, a control block is generated identifying the first route vector in the route associated with the command. Each station has a work queue containing control blocks, which the station retrieves and processes sequentially. The control block is first sent to the work queue of the station to perform the first operation. When the station gets to the control block, it performs the operation required by the route vector, modifies the control block to identify the next route vector in the sequence, and transfers the control block to the work queue of the station to perform the operation required by the next route vector in the route.

    摘要翻译： 一种用于响应于命令协调多处理器系统中的多个处理器的操作的控制装置。 每个命令与包括路由向量序列的路由相关联，每个路由向量标识要执行的执行命令的操作以及进程或站来执行路由向量。 响应于接收到命令，生成识别与该命令相关联的路由中的第一路由向量的控制块。 每个工作站都有一个包含控制块的工作队列，该工作站将按顺序检索和处理。 控制块首先被发送到站的工作队列以执行第一操作。 当站到达控制块时，执行路由向量所需的操作，修改控制块以识别序列中的下一个路由向量，并将控制块传送到站的工作队列，以执行所需的操作 由路由中的下一个路由向量。

    Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems
    3.
    发明授权
    Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems 失效
    一对处理器之间的接口，例如数据处理系统中的主机和外围控制处理器

    公开(公告)号：US4449182A

    公开(公告)日：1984-05-15

    申请号：US308826

    申请日：1981-10-05

    申请人： Barry L. Rubinson ,  Edward A. Gardner ,  William A. Grace ,  Richard F. Lary ,  Dale R. Keck

    发明人： Barry L. Rubinson ,  Edward A. Gardner ,  William A. Grace ,  Richard F. Lary ,  Dale R. Keck

    IPC分类号： G06F15/16 ,  G06F5/06 ,  G06F9/445 ,  G06F9/52 ,  G06F12/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/38 ,  G06F15/167 ,  G06F15/173 ,  G06F15/177 ,  H04L13/08 ,  G06F9/46

    CPC分类号： G06F9/4405 ,  G06F13/126 ,  G06F15/17356 ,  G06F15/177

    摘要： An interface mechanism (10) between two processors, such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40), and utilizing a set of data structures employing a dedicated communications region (80A) in host memory (80). Interprocessor commands and responses are communicated as packets over an I/O bus (60) of the host (70), to and from the communication region (80A), through a pair of ring-type queues (80D) and (80E). The entry of each ring location (e.g., 132, 134, 136, 138) points to another location in the communications region where a command or response is placed. The filling and emptying of ring entries (132-138) is controlled through the use of an `ownership` byte or bit (278) associated with each entry. The ownership bit (278) is placed in a first state when the message source (70 or 31) has filled the entry and in a second state when the entry has been emptied. Each processor keeps track of the rings' status, to prevent the sending of more messages than the rings can hold. These rings permit each processor to operate at its own speed, without creating race conditions and obviate the need for hardware interlock capability on the I/O bus (60).

    摘要翻译： 在用于大容量存储设备（40）的智能控制器（30）中的诸如主机处理器（70）和处理器（31）的两个处理器之间的接口机构（10），并且利用采用专用通信的一组数据结构 主机存储器（80）中的区域（80A）。 处理器的命令和响应通过主机（70）的I / O总线（60）通过一对环型队列（80D）和（80E）传送到通信区域（80A）和/或从通信区域（80A）传送。 每个环位置的输入（例如，132,134,136,138）指向放置命令或响应的通信区域中的另一位置。 通过使用与每个条目相关联的“所有权”字节或位（278）来控制环形条目（132-138）的填充和排空。 当消息源（70或31）已经填充条目时，所有权位（278）被置于第一状态，并且当条目被清空时处于第二状态。 每个处理器跟踪环的状态，以防止发送比环可以容纳更多的消息。 这些环允许每个处理器以自己的速度运行，而不会产生竞争条件，从而避免了I / O总线（60）上硬件互锁能力的需要。

    Secondary storage facility employing serial communications between drive and controller
    6.
    发明授权
    Secondary storage facility employing serial communications between drive and controller 失效
    二级存储设备采用驱动器和控制器之间的串行通信

    公开(公告)号：US4825406A

    公开(公告)日：1989-04-25

    申请号：US946891

    申请日：1987-03-20

    申请人： Robert G. Bean ,  Michael E. Beckman ,  Barry L. Rubinson ,  Edward A. Gardner ,  O. Winston Sergeant ,  Peter T. McLean

    发明人： Robert G. Bean ,  Michael E. Beckman ,  Barry L. Rubinson ,  Edward A. Gardner ,  O. Winston Sergeant ,  Peter T. McLean

    IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F13/42 ,  G06F13/12

    CPC分类号： G06F13/423 ,  G06F11/0727 ,  G06F11/0793 ,  G06F3/0601 ,  G06F2003/0692 ,  G06F2003/0697

    摘要： In a system including a plurality of mass storage devices at least one of which includes first and second ports, a plurality of controllers and cables coupling the ports to various ones of the controllers and in which each device can only be on-line through one port at a time, state information is sent from the on-line port of each device to a first controller to which it is coupled until a predetermined command from the controller to the on-line port is sent by the first controller. The device responds to the predetermined command by discontinuing the sending of state information from the on-line port to the first controller, and sending a state available signal from the other port to the second controller while maintaining the actual state of said device unchanged, permitting the other controller to interrogate the device as an aid in determining system topology.

    摘要翻译： 在包括多个大容量存储设备的系统中，其中至少一个包括第一和第二端口，多个控制器和电缆将端口耦合到各种控制器，并且其中每个设备只能通过一个端口在线 一次，将状态信息从每个设备的在线端口发送到其所耦合的第一控制器，直到由控制器到在线端口的预定命令由第一控制器发送。 设备通过中断将状态信息从在线端口发送到第一控制器来响应预定命令，并且将状态可用信号从另一端口发送到第二控制器，同时保持所述设备的实际状态不变，允许 另一个控制器询问设备，以帮助确定系统拓扑。

    Secondary storage facility employing serial communications between drive and controller
    7.
    发明授权
    Secondary storage facility employing serial communications between drive and controller 失效
    二级存储设备采用驱动器和控制器之间的串行通信

    公开(公告)号：US4811279A

    公开(公告)日：1989-03-07

    申请号：US58591

    申请日：1987-03-09

    申请人： Robert G. Bean ,  Michael E. Beckman ,  Barry L. Rubinson ,  Edward A. Gardner ,  O. Winston Sergeant ,  Peter T. McLean

    发明人： Robert G. Bean ,  Michael E. Beckman ,  Barry L. Rubinson ,  Edward A. Gardner ,  O. Winston Sergeant ,  Peter T. McLean

    IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/423 ,  G06F11/0727 ,  G06F11/0793 ,  G06F3/0601 ,  G06F2003/0692 ,  G06F2003/0697

    摘要： A radial bus for use in a secondary storage subsystem, between a mass storage drive and controller. The bus has four unidirectional bit-serial channels, two for carrying signals from drive to controllers. One channel carries real-time drive state information to the controller; another carries real-time controller state information to the drive. The state information is a sequence of multiplexed bits sent in continuous repetition. Most status variables are represented as a single bit in a specific place in the sequence; the set of status variables defining drive state or controller state, as the case may be, is thus provided by a sequence of bits. When such a bit changes state, a potential change of status has occurred; the change is required to persist some number of repetition of the sequence before the state change is recognized, to avoid spuriously signalling a state change.

    摘要翻译： 用于辅助存储子系统中的径向母线，位于大容量存储驱动器和控制器之间。 该总线具有四个单向位串行通道，两个用于传送从驱动器到控制器的信号。 一个通道向控制器传送实时驱动状态信息; 另一个将实时控制器状态信息传送到驱动器。 状态信息是以连续重复发送的多路复用位序列。 大多数状态变量在序列中的特定位置表示为单个位; 因此，通过比特序列来提供定义驱动状态或控制器状态（视情况而定）的一组状态变量。 当这种状态发生变化时，状态发生了潜在的变化; 在识别状态改变之前，需要进行一些重复序列的改变，以避免虚假地发信号通知状态变化。