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1.发明授权
公开(公告)号：US6148359A
公开(公告)日：2000-11-14
申请号：US186597
申请日：1998-11-05
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches the bridge interface from the bridge or PCI bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the delay for the snoop phase or the possibility of defer or retry.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI-to-EISA桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 系统总线是超级管道，因为交易重叠。 在桥接器和主存储器之间允许快速突发事务，即，可以在不延迟或重试的情况下满足的请求被应用于系统总线，而不等待从目标获得响应。 地址范围（例如，系统存储器地址）被定义为快速突发范围，并且该范围内的任何地址与该范围之外的地址不同。 通过配置周期对桥进行编程，以建立此快速突发范围，在此范围内，已知无法接收到无序响应。 当事务从桥接器或PCI总线到达桥接口时，并且认识到地址在该范围内，则允许快速突发模式，并且允许写入地址彼此跟随，而没有窥探阶段的延迟 或延迟或重试的可能性。
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2.再颁专利公开(公告)号：USRE37980E1
公开(公告)日：2003-02-04
申请号：US09706883
申请日：2000-11-03
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 系统总线是超级管道，因为交易重叠。 在桥接器和主存储器之间允许快速突发事务，即，可以在不延迟或重试的情况下满足的请求被应用于系统总线，而不等待从目标获得响应。 地址范围（例如，系统存储器地址）被定义为快速突发范围，并且该范围内的任何地址与该范围之外的地址不同。 通过配置周期对桥进行编程，以建立此快速突发范围，在此范围内，已知无法接收到无序响应。 当事务从PCI总线到达桥接口时，并且认识到地址在快速突发范围内，则允许快速突发模式，并且可以发出写入或读取请求而不等待窥探阶段，因为 没有推迟或重试的可能性。
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公开(公告)号：US5835741A
公开(公告)日：1998-11-10
申请号：US777597
申请日：1996-12-31
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.
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公开(公告)号：US06557068B2
公开(公告)日：2003-04-29
申请号：US09747422
申请日：2000-12-22
IPC分类号： G06F1338
CPC分类号： G06F13/105
摘要： A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with current devices.
摘要翻译： 为数字计算机系统上的外围组件提供高速连接装置，方法和系统。 外围组件互连（PCI）规范用作扩展命令和属性集的基准。 扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。 扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。 传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。 扩展命令根据事务类型和扩展命令类型分为四组。 事务是字节计数或字节使能事务类型。 扩展命令类型是验证的或立即的。 一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，这些扩展命令将使用当前设备来预测。
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5.发明授权公开(公告)号：US06816934B2
公开(公告)日：2004-11-09
申请号：US10424896
申请日：2003-04-28
IPC分类号： G06F1336
CPC分类号： G06F13/4027 , G06F13/405
摘要： A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with current devices.
摘要翻译： 为数字计算机系统上的外围组件提供高速连接装置，方法和系统。 外围组件互连（PCI）规范用作扩展命令和属性集的基准。 扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。 扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。 传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。 扩展命令根据事务类型和扩展命令类型分为四组。 事务是字节计数或字节使能事务类型。 扩展命令类型是验证的或立即的。 一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，这些扩展命令将使用当前设备来预测。
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6.发明授权公开(公告)号：US07587542B2
公开(公告)日：2009-09-08
申请号：US11193590
申请日：2005-07-28
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/405
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.
摘要翻译： 在可以配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥接器的计算机系统中提供多用途核心逻辑芯片组，作为附加注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。
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公开(公告)号：US07464207B2
公开(公告)日：2008-12-09
申请号：US11192561
申请日：2005-07-29
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F13/405
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.
摘要翻译： 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。
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公开(公告)号：US07099986B2
公开(公告)日：2006-08-29
申请号：US10945003
申请日：2004-09-20
IPC分类号： G06F13/38
CPC分类号： G06F13/4027 , G06F13/405
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.
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公开(公告)号：US06266731B1
公开(公告)日：2001-07-24
申请号：US09148042
申请日：1998-09-03
IPC分类号： G06F1338
CPC分类号： G06F13/105
摘要： A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with current devices.
摘要翻译： 为数字计算机系统上的外围组件提供高速连接装置，方法和系统。 外围组件互连（PCI）规范用作扩展命令和属性集的基准。 扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。 扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。 传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。 扩展命令根据事务类型和扩展命令类型分为四组。 事务是字节计数或字节使能事务类型。 扩展命令类型是验证的或立即的。 一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，这些扩展命令将使用当前设备来预测。
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10.发明授权Data bus agent including a storage medium between a data bus and the bus agent device 失效数据总线代理，包括数据总线和总线代理设备之间的存储介质
公开(公告)号：US06067590A
公开(公告)日：2000-05-23
申请号：US873636
申请日：1997-06-12
CPC分类号： G06F13/405
摘要： A system and method of transferring data on a data bus is disclosed. The system includes a data bus agent having a storage medium connectable to a data bus and arranged to store data and a bus agent device adapted to receive data from the storage medium. The method includes driving a signal on a data bus by a first bus agent, sampling the signal at a second bus agent, storing the sampled signal in a storage medium associated with the second bus agent, and processing the stored signal at the second bus agent.
摘要翻译： 公开了一种在数据总线上传送数据的系统和方法。 该系统包括具有可连接到数据总线并被布置成存储数据的存储介质和适于从存储介质接收数据的总线代理设备的数据总线代理。 该方法包括通过第一总线代理在数据总线上驱动信号，在第二总线代理处采样信号，将采样信号存储在与第二总线代理相关联的存储介质中，以及在第二总线代理处理存储的信号 。
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