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公开(公告)号：US20080222389A1
公开(公告)日：2008-09-11
申请号：US11682867
申请日：2007-03-06
IPC分类号： G06F15/76
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译： 一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。 该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器间消息信息。 系统包括一致性互连和处理器。 处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。 该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息生成中断。
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公开(公告)号：US07941499B2
公开(公告)日：2011-05-10
申请号：US11682867
申请日：2007-03-06
IPC分类号： G06F15/167
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译： 一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。 该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器内消息信息。 系统包括一致性互连和处理器。 处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。 该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息来生成中断。
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公开(公告)号：US07702881B2
公开(公告)日：2010-04-20
申请号：US11669804
申请日：2007-01-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0284
摘要： A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.
摘要翻译： 处理设备包括被配置为存储与第一地址空间相关联的第一值的第一存储位置，被配置为存储与第二地址空间相关联的第二值的第二存储位置以及被配置为存储与第二地址空间相关联的第三值的第三存储位置 具有第三个地址空间。 处理装置还包括存储器管理单元，其包括被配置为接收与数据传送操作相关联的第一地址值的第一输入，被配置为接收与数据传送操作相关联的标识符的第二输入以及地址空间选择模块 被配置为基于所述标识符从所述第一值，所述第二值和所述第三值中识别选择值。 存储器管理模块还包括地址修改模块，该地址修改模块被配置为基于第一地址值和选择值生成第二地址值。
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公开(公告)号：US20080183943A1
公开(公告)日：2008-07-31
申请号：US11669804
申请日：2007-01-31
IPC分类号： G06F12/02
CPC分类号： G06F12/0284
摘要： A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.
摘要翻译： 处理设备包括被配置为存储与第一地址空间相关联的第一值的第一存储位置，被配置为存储与第二地址空间相关联的第二值的第二存储位置以及被配置为存储与第二地址空间相关联的第三值的第三存储位置 具有第三个地址空间。 处理装置还包括存储器管理单元，其包括被配置为接收与数据传送操作相关联的第一地址值的第一输入，被配置为接收与数据传送操作相关联的标识符的第二输入以及地址空间选择模块 被配置为基于所述标识符从所述第一值，所述第二值和所述第三值中识别选择值。 存储器管理模块还包括地址修改模块，该地址修改模块被配置为基于第一地址值和选择值生成第二地址值。
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