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公开(公告)号：US20080071783A1
公开(公告)日：2008-03-20
申请号：US11766704
申请日：2007-06-21
IPC分类号： G06F17/30
CPC分类号： H04L63/1416 , G06F21/55
摘要： A computer software product, methods and apparatus for target report generation are provided. In one embodiment, a trigger pattern is derived from at least one target pattern. Locations within a data set containing the trigger pattern are identified and a target report is generated. In another embodiment, a computing apparatus is provided that produces reports by deriving a trigger pattern, identifying locations within a dataset where the trigger patterns exist and generating a report. In a further embodiment, a computer software product is provided that configures an apparatus to generate a target report. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
摘要翻译： 提供了一种用于目标报告生成的计算机软件产品，方法和装置。 在一个实施例中，从至少一个目标图案导出触发图案。 识别包含触发模式的数据集中的位置，并生成目标报告。 在另一个实施例中，提供了一种计算装置，其通过导出触发模式来产生报告，识别存在触发模式的数据集内的位置并生成报告。 在另一实施例中，提供了一种配置设备以生成目标报告的计算机软件产品。 本摘要仅用于遵守允许读者快速确定本文所包含的披露的主题的抽象要求规则。 本摘要以明确的理解提交，不会用于解释或限制权利要求的范围或含义。
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公开(公告)号：US09342334B2
公开(公告)日：2016-05-17
申请号：US13530793
申请日：2012-06-22
CPC分类号： G06F9/4552 , G06F11/3644 , G06F17/5022 , G06F2217/86
摘要： A system and method for simulating new instructions without compiler support for the new instructions. A simulator detects a given region in code generated by a compiler. The given region may be a candidate for vectorization or may be a region already vectorized. In response to the detection, the simulator suspends execution of a time-based simulation. The simulator then serially executes the region for at least two iterations using a functional-based simulation and using instructions with operands which correspond to P or less lanes of single-instruction-multiple-data (SIMD) execution. The value P is a maximum number of lanes of SIMD exection supported both by the compiler. The simulator stores checkpoint state during the serial execution. In response to determining no inter-iteration memory dependencies exist, the simulator returns to the time-based simulation and resumes execution using N-wide vector instructions.
摘要翻译： 用于模拟新指令的系统和方法，无需编译器支持新指令。 模拟器会检测编译器生成的代码中的给定区域。 给定区域可以是向量化的候选者，或者可以是已经向量化的区域。 响应于该检测，模拟器暂停执行基于时间的模拟。 仿真器然后使用基于功能的仿真并使用具有对应于单指令多数据（SIMD）执行的P或更少通道的操作数的指令来串行地执行该区域至少两次迭代。 值P是由编译器支持的SIMD exection的最大通道数。 模拟器在串行执行期间存储检查点状态。 响应于确定不存在迭代存储器依赖性，仿真器返回到基于时间的仿真，并使用N宽向量指令恢复执行。
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公开(公告)号：US20130346058A1
公开(公告)日：2013-12-26
申请号：US13530793
申请日：2012-06-22
IPC分类号： G06F9/45
CPC分类号： G06F9/4552 , G06F11/3644 , G06F17/5022 , G06F2217/86
摘要： A system and method for simulating new instructions without compiler support for the new instructions. A simulator detects a given region in code generated by a compiler. The given region may be a candidate for vectorization or may be a region already vectorized. In response to the detection, the simulator suspends execution of a time-based simulation. The simulator then serially executes the region for at least two iterations using a functional-based simulation and using instructions with operands which correspond to P or less lanes of single-instruction-multiple-data (SIMD) execution. The value P is a maximum number of lanes of SIMD exection supported both by the compiler. The simulator stores checkpoint state during the serial execution. In response to determining no inter-iteration memory dependencies exist, the simulator returns to the time-based simulation and resumes execution using N-wide vector instructions.
摘要翻译： 用于模拟新指令的系统和方法，无需编译器支持新指令。 模拟器会检测编译器生成的代码中的给定区域。 给定区域可以是向量化的候选者，或者可以是已经向量化的区域。 响应于该检测，模拟器暂停执行基于时间的模拟。 仿真器然后使用基于功能的仿真并使用具有对应于单指令多数据（SIMD）执行的P或更少通道的操作数的指令来串行地执行该区域至少两次迭代。 值P是由编译器支持的SIMD exection的最大通道数。 模拟器在串行执行期间存储检查点状态。 响应于确定不存在迭代存储器依赖性，仿真器返回到基于时间的仿真，并使用N宽向量指令恢复执行。
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公开(公告)号：US20120124297A1
公开(公告)日：2012-05-17
申请号：US12945226
申请日：2010-11-12
CPC分类号： G06F12/0817
摘要： A method includes bypassing a global coherence operation that maintains global memory coherence between a plurality of local memories associated with a plurality of corresponding processors. The bypassing is in response to an address of a memory request being associated with a local memory coherence domain. The method includes accessing a memory location associated with the local memory coherence domain according to the memory request in response to the address being associated with the local memory coherence domain.
摘要翻译： 一种方法包括绕过保持与多个相应处理器相关联的多个本地存储器之间的全局存储器相干性的全局相干操作。 旁路是响应于与本地存储器相干域相关联的存储器请求的地址。 该方法包括响应于与本地存储器相干域相关联的地址，根据存储器请求访问与本地存储器相干域相关联的存储器位置。
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公开(公告)号：US08812786B2
公开(公告)日：2014-08-19
申请号：US13275538
申请日：2011-10-18
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0813 , G06F12/084
摘要： A system and method of providing directory cache coherence are disclosed. The system and method may include tracking the coherence state of at least one cache block contained within a region using a global directory, providing at least one region level sharing information about the least one cache block in the global directory, and providing at least one block level sharing information about the at least one cache block in the global directory. The tracking of the provided at least one region level sharing information and the provided at least one block level sharing information may organize the coherence state of the at least one cache block and the region.
摘要翻译： 公开了提供目录高速缓存一致性的系统和方法。 该系统和方法可以包括使用全局目录跟踪包含在区域内的至少一个高速缓存块的相干状态，提供关于全局目录中的至少一个高速缓存块的至少一个区域级共享信息，以及提供至少一个块 关于全局目录中的至少一个高速缓存块的级别共享信息。 所提供的至少一个区域级共享信息的跟踪和所提供的至少一个块级共享信息可以组织至少一个高速缓存块和该区域的相干状态。
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6.发明申请DATA PREFETCHER MECHANISM WITH INTELLIGENT DISABLING AND ENABLING OF A PREFETCHING FUNCTION 审中-公开具有智能禁用和启用预先功能的数据预选机制公开(公告)号：US20130013867A1
公开(公告)日：2013-01-10
申请号：US13177419
申请日：2011-07-06
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/502 , Y02D10/13
摘要： A data prefetcher includes a controller to control operation of the data prefetcher. The controller receives data associated with cache misses and data associated with events that do not rely on a prefetching function of the data prefetcher. The data prefetcher also includes a counter to maintain a count associated with the data prefetcher. The count is adjusted in a first direction in response to detection of a cache miss, and in a second direction in response to detection of an event that does not rely on the prefetching function. The controller disables the prefetching function when the count reaches a threshold value.
摘要翻译： 数据预取器包括控制器来控制数据预取器的操作。 控制器接收与高速缓存未命中相关联的数据和与不依赖于数据预取器的预取功能的事件相关联的数据。 数据预取器还包括计数器以维持与数据预取器相关联的计数。 响应于检测到高速缓存未命中而在第一方向上调整计数，并且响应于不依赖于预取功能的事件的检测而在第二方向上调整计数。 当计数达到阈值时，控制器将禁用预取功能。
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公开(公告)号：US07587663B2
公开(公告)日：2009-09-08
申请号：US11439485
申请日：2006-05-22
IPC分类号： G06F11/14
CPC分类号： G06F11/1484 , G06F11/16
摘要： A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.
摘要翻译： 一种检测计算机系统中的错误的技术。 更具体地，本发明的至少一个实施例涉及使用冗余虚拟机和比较逻辑来检测在计算机系统中的输入/输出（I / O）操作中发生的错误。
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公开(公告)号：US20130007373A1
公开(公告)日：2013-01-03
申请号：US13173441
申请日：2011-06-30
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F2212/502
摘要： A method, apparatus, and system for replacing at least one cache region selected from a plurality of cache regions, wherein each of the regions is composed of a plurality of blocks is disclosed. The method includes applying a first algorithm to the plurality of cache regions to limit the number of potential candidate regions to a preset value, wherein the first algorithm assesses the ability of a region to be replaced based on properties of the plurality of blocks associated with that region; and designating at least one of the limited potential candidate regions as a victim based region level information associated with each of the limited potential candidate regions.
摘要翻译： 一种用于替换从多个高速缓存区域中选择的至少一个高速缓存区域的方法，装置和系统，其中每个区域由多个块组成。 该方法包括将第一算法应用于多个高速缓存区域以将潜在候选区域的数量限制为预设值，其中第一算法基于与该相关联的多个块相关联的属性来评估区域被替换的能力 地区; 以及将所述有限潜在候选区域中的至少一个指定为与所述有限潜在候选区域中的每一个相关联的基于受害者的区域级别信息。
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公开(公告)号：US20110314255A1
公开(公告)日：2011-12-22
申请号：US12817945
申请日：2010-06-17
CPC分类号： G06F15/17337
摘要： A processor and method for broadcasting data among a plurality of processing cores is disclosed. The processor includes a plurality of processing cores connected by point-to-point connections. A first of the processing cores includes a router that includes at least an allocation unit and an output port. The allocation unit is configured to determine that respective input buffers on at least two others of the processing cores are available to receive given data. The output port is usable by the router to send the given data across one of the point-to-point connections. The router is configured to send the given data contingent on determining that the respective input buffers are available. Furthermore, the processor is configured to deliver the data to the at least two other processing cores in response to the first processing core sending the data once across the point-to-point connection.
摘要翻译： 公开了一种用于在多个处理核心之间广播数据的处理器和方法。 处理器包括通过点对点连接连接的多个处理核心。 处理核心中的第一个包括至少包括分配单元和输出端口的路由器。 配置单元被配置为确定处理核中的至少两个其他输入缓冲器可用于接收给定数据。 输出端口可用于路由器通过点对点连接之一发送给定数据。 路由器被配置为在确定相应的输入缓冲器可用的情况下发送给定数据。 此外，处理器被配置为响应于第一处理核心通过点对点连接发送数据一次将数据传送到至少两个其他处理核心。
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公开(公告)号：US07373548B2
公开(公告)日：2008-05-13
申请号：US10651523
申请日：2003-08-29
IPC分类号： G06F11/00
CPC分类号： G06F11/1482
摘要： Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.
摘要翻译： 基于日志的硬件恢复。 系统的检查点状态包括体系结构寄存器值和存储器。 检查点由生成检查点时的体系结构寄存器文件值的副本组成。 维护非确定性事件的有序日志，以便重复响应以模拟完整的检查点以进行错误恢复。 当处理器检测到错误时，处理器从上一个检查点重新加载状态，并从日志重复非确定性事件。
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