公开(公告)号：US20130343501A1

公开(公告)日：2013-12-26

申请号：US13529366

申请日：2012-06-21

申请人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

发明人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

IPC分类号： H04L7/00

CPC分类号： H04N21/6118 ,  H04L25/14 ,  H04L27/34 ,  H04N21/4382 ,  H04N21/4385 ,  H04N21/4622 ,  H04N21/631

摘要： A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to many up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

摘要翻译： 描述了一种系统和方法来提供基于DOCSIS标准的下一代电缆网关/调制解调器，其具有同步组合物理层中的信道以增加用于同轴电缆数据传输的总比特率的方案。 系统和方法将发射机处的与多个通道相关联的计数器（包括连续性计数器）同步到零，然后允许各个通道上的计数器单独增加。 在接收机处，基于与每个信道相关联的计数器提供的信息，各个信道的各个信道延迟将因此被识别。 接收器处的缓冲器被通知并用于将多个通道中的一个或多个单独地延迟到许多向上的连续性计数器值。 以这种方式，缓冲器用于基本上均衡各个信道中的延迟，连续性计数器表示用于指定单独信道的各个延迟的机制。

公开(公告)号：US08781052B2

公开(公告)日：2014-07-15

申请号：US13529366

申请日：2012-06-21

申请人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

发明人： Bernard Arambepola ,  Shaul Shulman ,  Naor Goldman ,  Amos Klimker ,  Noam Tal

IPC分类号： H04J3/06 ,  H04L7/04 ,  H04L7/00

CPC分类号： H04N21/6118 ,  H04L25/14 ,  H04L27/34 ,  H04N21/4382 ,  H04N21/4385 ,  H04N21/4622 ,  H04N21/631

摘要： A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

摘要翻译： 描述了一种系统和方法来提供基于DOCSIS标准的下一代电缆网关/调制解调器，其具有同步组合物理层中的信道以增加用于同轴电缆数据传输的总比特率的方案。 系统和方法将发射机处的与多个通道相关联的计数器（包括连续性计数器）同步到零，然后允许各个通道上的计数器单独增加。 在接收机处，基于与每个信道相关联的计数器提供的信息，各个信道的各个信道延迟将因此被识别。 接收器处的缓冲器被通知并用于单独延迟多个通道中的一个或多个以结束连续性计数器值。 以这种方式，缓冲器用于基本上均衡各个信道中的延迟，连续性计数器表示用于指定单独信道的各个延迟的机制。

公开(公告)号：US09225499B2

公开(公告)日：2015-12-29

申请号：US13976468

申请日：2012-03-28

申请人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

发明人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

IPC分类号： H04L5/14 ,  H04L1/00

CPC分类号： H04L5/14 ,  H04L1/0041 ,  H04L1/0083 ,  H04L12/2801 ,  H04L27/0002 ,  H04M11/00 ,  H04N21/6118 ,  H04N21/6168

摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

摘要翻译： 一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。 例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数 确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

公开(公告)号：US20130272357A1

公开(公告)日：2013-10-17

申请号：US13976468

申请日：2012-03-28

申请人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

发明人： Shaul Shulman ,  Dmitrii A. Loukianov ,  Naor Goldman ,  Bernard Arambepola

IPC分类号： H04L5/14

CPC分类号： H04L5/14 ,  H04L1/0041 ,  H04L1/0083 ,  H04L12/2801 ,  H04L27/0002 ,  H04M11/00 ,  H04N21/6118 ,  H04N21/6168

摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

摘要翻译： 一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。 例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数 确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

公开(公告)号：US07746965B2

公开(公告)日：2010-06-29

申请号：US11772461

申请日：2007-07-02

申请人： Alon Elhanati ,  Liran Brecher ,  Naor Goldman ,  Noam Tal ,  Shaul Klein

发明人： Alon Elhanati ,  Liran Brecher ,  Naor Goldman ,  Noam Tal ,  Shaul Klein

IPC分类号： H04L27/08 ,  H04B1/16

CPC分类号： H03G3/3052 ,  H03G3/3089

摘要： One embodiment of the present invention includes a method for controlling a gain of a wideband signal. The method comprises adding a virtual channel to the wideband signal, the wideband signal comprising at least one channel. The method also comprises monitoring an output power associated with the wideband signal that includes the at least one channel and the virtual channel. The method further comprises setting a gain factor to achieve a predetermined output power of the wideband signal and amplifying the wideband signal based on the gain factor.

摘要翻译： 本发明的一个实施例包括一种用于控制宽带信号的增益的方法。 所述方法包括向所述宽带信号添加虚拟信道，所述宽带信号包括至少一个信道。 该方法还包括监视与包括至少一个信道和虚拟信道的宽带信号相关联的输出功率。 该方法还包括设置增益因子以实现宽带信号的预定输出功率，并且基于增益因子放大宽带信号。

公开(公告)号：US20080181283A1

公开(公告)日：2008-07-31

申请号：US11772461

申请日：2007-07-02

申请人： Alon Elhanati ,  Liran Brecher ,  Naor Goldman ,  Noam Tal ,  Shaul Klein

发明人： Alon Elhanati ,  Liran Brecher ,  Naor Goldman ,  Noam Tal ,  Shaul Klein

IPC分类号： H04B1/00

CPC分类号： H03G3/3052 ,  H03G3/3089

摘要： One embodiment of the present invention includes a method for controlling a gain of a wideband signal. The method comprises adding a virtual channel to the wideband signal, the wideband signal comprising at least one channel. The method also comprises monitoring an output power associated with the wideband signal that includes the at least one channel and the virtual channel. The method further comprises setting a gain factor to achieve a predetermined output power of the wideband signal and amplifying the wideband signal based on the gain factor.

摘要翻译： 本发明的一个实施例包括一种用于控制宽带信号的增益的方法。 所述方法包括向所述宽带信号添加虚拟信道，所述宽带信号包括至少一个信道。 该方法还包括监视与包括至少一个信道和虚拟信道的宽带信号相关联的输出功率。 该方法还包括设置增益因子以实现宽带信号的预定输出功率，并且基于增益因子放大宽带信号。

公开(公告)号：US08159377B2

公开(公告)日：2012-04-17

申请号：US12872043

申请日：2010-08-31

申请人： Naor Goldman ,  Noam Tal ,  Yonina Eldar ,  Charles Sestok ,  Efrat Levy

发明人： Naor Goldman ,  Noam Tal ,  Yonina Eldar ,  Charles Sestok ,  Efrat Levy

IPC分类号： H03M1/06

CPC分类号： H03M1/0624 ,  H03M1/1215

摘要： A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit also continually calculates the timing skew of each of the plurality of ADCs, except the reference ADC, as the sum of an immediately previous estimate of the timing skew of each ADC, except the reference ADC, and a product of a function of the gradient of each of the plurality of ADCs, except the reference ADC, and a step size, The correction unit continually corrects the output of each of the plurality of ADCs, except the reference ADC, based on the estimates of the timing skew of each of the plurality of ADCs, except the reference ADC. Eventually, the timing skew estimation system determines a converged estimate of the timing skew of each of the plurality of ADCs, except the reference ADC. A method of estimating timing skew and timing skew estimation circuitry are also disclosed.

摘要翻译： 公开了一种包括多个交错模数转换器电路（ADC），定时失配估计单元和校正单元的定时偏移估计系统。 定时失配估计单元计算多个ADC中的每一个之间的相关性。 然后，定时失配估计单元计算除了参考ADC之外的多个ADC中的每一个的成本函数。 定时失配估计单元进一步计算除了参考ADC之外的多个ADC中的每一个的梯度。 定时失配估计单元还连续地计算除了参考ADC之外的多个ADC中的每一个的定时偏差，作为除了参考ADC之外的每个ADC的定时偏差的紧接的先前估计之和和a的乘积之和 除了参考ADC之外的多个ADC中的每一个的梯度的函数以及步长。校正单元基于定时偏差的估计来连续地校正除了参考ADC之外的多个ADC中的每一个的输出 的多个ADC中的每一个，除了参考ADC。 最后，定时偏移估计系统确定除了参考ADC之外的多个ADC中的每一个的定时偏差的收敛估计。 还公开了一种估计定时偏移和定时偏差估计电路的方法。

公开(公告)号：US20140185657A1

公开(公告)日：2014-07-03

申请号：US13728022

申请日：2012-12-27

申请人： Bernard Arambepola ,  Murat Badem ,  Parveen K. Shukla ,  Sahan Gamage ,  Thushara Hewavithana ,  Naor Goldman

发明人： Bernard Arambepola ,  Murat Badem ,  Parveen K. Shukla ,  Sahan Gamage ,  Thushara Hewavithana ,  Naor Goldman

IPC分类号： H04L27/06

CPC分类号： H04L27/06 ,  H03M13/1515 ,  H03M13/451 ,  H03M13/453 ,  H04L1/0045 ,  H04L1/0047 ,  H04L1/0057 ,  H04L27/38

摘要： A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-QAM, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 dB relaxing design considerations and specifications for other components in the system including for the tuner. A soft-RS-symbol generation scheme is provided to enable soft-input RC decoding in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. A typical receiver hardware requirement in an FEC module to implement the disclosed scheme may be comparatively modest, e.g., on an order of approximately 50K gates.

摘要翻译： 提供了一种用于实现软的里德 - 所罗门（RS）解码方案，技术或算法以改善电缆调制解调器和电缆网关中的物理层性能的系统和方法。 在1024-QAM中，提供了一种接收机，其中信噪比降低了包括用于调谐器的系统中其他部件的至少约1dB的松弛设计考虑和规格。 提供软RS符号生成方案以在连接到QAM解调器的前向纠错（FEC）模块中实现软输入RC解码。 实现RS解码方案，而不会使硬件或处理开销显着复杂化。 用于实现所公开的方案的FEC模块中的典型接收机硬件要求可以是相对适中的，例如大约50K门的量级。

公开(公告)号：US20070223597A1

公开(公告)日：2007-09-27

申请号：US11689038

申请日：2007-03-21

申请人： Naor Goldman ,  Naftali Sommer

发明人： Naor Goldman ,  Naftali Sommer

IPC分类号： H04B14/06 ,  H04L5/12

CPC分类号： H04B14/06 ,  H04L1/0057 ,  H04L25/067 ,  H04L27/3845

摘要： A novel apparatus and method of differential decoding for use in a communication system such as a cable system. The differential decoding mechanism of the present invention enables the use of the Chase algorithm for Reed Solomon (RS) codes (i.e. non-binary codes). The mechanism is well suited for use in systems employing QAM data modulation/demodulation techniques and that also incorporate use of a differential encoder such as in DOCSIS capable cable modem systems. The differential decoding mechanism is operative to analyze the input to the differential decoder and adjust the decoding action accordingly. The mechanism generates the first and second candidate constellation points needed by the Chase algorithm. Considering the differential encoding, there are four possible constellation candidates. The differential decoder reduces these four possible options to two by eliminating from consideration two of them. Depending on the number of symbols to be improved by the Chase algorithm, this reduction can potentially reduce the number of options significantly.

摘要翻译： 一种用于诸如电缆系统的通信系统中使用的差分解码的新型装置和方法。 本发明的差分解码机构能够使用Chase算法用于里德所罗门（RS）码（即非二进制码）。 该机制非常适用于采用QAM数据调制/解调技术的系统，并且还结合使用差分编码器，如DOCSIS能力的电缆调制解调器系统。 差分解码机构用于分析差分解码器的输入并相应地调整解码动作。 该机制产生Chase算法所需的第一和第二候选星座点。 考虑到差分编码，有四种可能的星座候选。 差分解码器将这四种可能的选择从两种方案中消除了考虑。 根据Chase算法要改进的符号数量，这种减少可以显着地减少选项数量。

公开(公告)号：US08677435B2

公开(公告)日：2014-03-18

申请号：US12323928

申请日：2008-11-26

申请人： Ziv Kfir ,  Efrat Levy ,  Naor Goldman

发明人： Ziv Kfir ,  Efrat Levy ,  Naor Goldman

IPC分类号： H04N7/173

CPC分类号： H04N7/17309 ,  H04L12/2801 ,  H04N7/102 ,  H04N17/004 ,  H04N21/44209 ,  H04N21/6118 ,  H04N21/6168 ,  H04N21/6582

摘要： A novel apparatus for and method of upstream power control for multiple transmit channels. The invention is particularly useful in environments that include two level amplification, wherein the first level corresponds to each channel separately and the second level corresponds to the joint sum of all the channels. When working with two-level amplification, changing the joint sum amplification is permitted during specific time periods known as “CMTS re-configuration time” in the DOCSIS specification. The mechanism functions to maintain an optimal transmit power operating point of the PGA using self-configuration without any need to receive permission from an exterior control entity such as the cable head-end thus bypassing the prior art requirement of waiting for a global reconfiguration time from the CMTS (i.e. when the specification assures that there is sufficient time to change the PGA gain). This can be achieved with high confidence if there is sufficient quiet time (which is calculated) to perform the self-configuration of the PGA within a specific period of time.

摘要翻译： 一种用于多个发射信道的上行功率控制的新型装置和方法。 本发明在包括两级放大的环境中特别有用，其中第一级分别对应于每个通道，第二级对应于所有通道的联合和。 当使用两级放大时，在DOCSIS规范中称为“CMTS重新配置时间”的特定时间段内允许更改联合和放大。 该机制用于使用自配置来保持PGA的最佳发射功率工作点，而不需要从诸如电缆头端的外部控制实体接收许可，从而绕过等待全局重新配置时间的现有技术要求 CMTS（即当规范确保有足够的时间来改变PGA增益时）。 如果在特定时间段内有足够的安静时间（被计算）来执行PGA的自配置，则可以以高置信度来实现。