Device and method for inducing vascular injury and/or blockage in an animal model
    2.
    发明申请
    Device and method for inducing vascular injury and/or blockage in an animal model 失效
    用于在动物模型中诱导血管损伤和/或阻塞的装置和方法

    公开(公告)号:US20060142746A1

    公开(公告)日:2006-06-29

    申请号:US10538548

    申请日:2003-12-11

    IPC分类号: A61B18/18

    摘要: Ultrashort laser pulses are used to induce photodisruptive breakdown in vasculature in an animal to controllably produce hemorrhage, thrombosis or breach of the blood-brain barrier in individual, specifically-targeted blood vessels. Damage is limited to the targeted vessels such that neighboring vessels exhibit no signs of vascular damage, including vessels directly above and directly below the targeted vessel. Ultrashort laser pulses of lower energy are also used to observe and quantify the baseline and altered states of blood flow. Observation and measurement may be performed by TPLSM, OCT or other known techniques, providing a real-time, in vivo model for the dynamics and effects of vascular injury.

    摘要翻译: 超短脉冲激光脉冲被用于诱发动物脉管系统中的光破坏性破坏,以可控地产生出血,血栓形成或破坏个体特异性靶向血管中的血脑屏障。 损害局限于目标船只,使相邻船只没有血管损伤迹象,包括直接位于目标船只正下方的血管。 较低能量的超短脉冲激光脉冲也用于观察和定量血流的基线和改变的状态。 观察和测量可以通过TPLSM,OCT或其他已知技术进行,为血管损伤的动力学和影响提供实时的体内模型。

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体封装及其制造方法

    公开(公告)号:US20110201159A1

    公开(公告)日:2011-08-18

    申请号:US13123385

    申请日:2009-09-25

    IPC分类号: H01L21/60

    摘要: A semiconductor package 10 comprising: terminals 14 electrically connected to a semiconductor device 11; and a resin 15 for sealing a part of the terminals 14 and the device 11; wherein an electrolytic plating layer 19 of Ag, Sn, or Ni is formed on each of bottom surfaces 17 of the terminals 14 partly projecting from the resin 15; an electroless plating layer 22 of Ni, Sn, Ag, Ag/Au, Ni/Au, Ni/Ag, Ni/Pd/Au, or Ni/Pd/Ag is formed thereon; and an electroless plating layer 22 comprising the same material as the electroless plating layer 22 previously formed on the bottom surface 17 of the protruding terminal 14, is formed on each lateral surfaces 20 of the protruding terminals 14. This configuration enables a lead frame material 32 to be etched from its bottom surface to separate the terminals 14 from each other, thereby preventing corrosion due to oxidation of the lateral surfaces (standoff sides) of the terminals 14 exposed by the etching, and further reducing a total manufacturing cost.

    摘要翻译: 一种半导体封装10,包括:电连接到半导体器件11的端子14; 以及用于密封端子14和装置11的一部分的树脂15; 其中,在从树脂15部分地突出的端子14的每个底面17上形成有Ag,Sn或Ni的电解电镀层19; 在其上形成Ni,Sn,Ag,Ag / Au,Ni / Au,Ni / Ag,Ni / Pd / Au或Ni / Pd / Ag的化学镀层22; 并且在突出端子14的每个侧表面20上形成包括与突出端子14的底表面17上预先形成的化学镀层22相同的材料的化学镀层22.这种构造使得引线框架材料32 从其底表面蚀刻以将端子14彼此分离,从而防止由蚀刻暴露的端子14的侧表面(支座侧)的氧化引起的腐蚀,并进一步降低总的制造成本。