公开(公告)号：US08219230B2

公开(公告)日：2012-07-10

申请号：US12797002

申请日：2010-06-09

申请人： Bhaskar Sinha ,  Ashish Patil ,  Ajay Deshpande ,  Alpana Sharma ,  Christine Zuzart ,  Sameer Kondejkar ,  Rajesh Jain ,  Nitin Umap ,  Rahul Rajadhyaksha

发明人： Bhaskar Sinha ,  Ashish Patil ,  Ajay Deshpande ,  Alpana Sharma ,  Christine Zuzart ,  Sameer Kondejkar ,  Rajesh Jain ,  Nitin Umap ,  Rahul Rajadhyaksha

IPC分类号： G06F19/00 ,  B29C45/00

CPC分类号： B29C45/7693 ,  G06F17/50 ,  G06F2217/41

摘要： A method of automatic manufacturability evaluation of plastic models comprises generation of a likely pulling direction, recognition of common features on plastic parts, and then applying manufacturability rules The manufacturability rules can be specified and customized through user specified rule parameters and depend upon the geometric parameters of the recognized features. A system comprises a user interface for selection and customization of DFX (Design for ‘X’) rules for evaluation of a design. The system includes a user interface integrated with a CAD system for receiving the CAD data and displaying the results to the user. Geometry analysis engines are integrated into the system, for extracting the various features and corresponding parameters required as input to the manufacturability rules. The system further involves extensible interfaces for rules and analysis engines which allows users to write their own customized rules and engines and integrate these into the CAD based DFX evaluation system.

摘要翻译： 塑料模型的自动制造性评估方法包括产生可能的拉动方向，识别塑料部件上的共同特征，然后应用可制造性规则可制造性规则可以通过用户指定的规则参数来指定和定制，并且取决于几何参数 公认的功能。 系统包括用于选择和定制DFX（用于'X'的设计）用于评估设计的规则的用户界面。 该系统包括与CAD系统集成的用于接收CAD数据并将结果显示给用户的用户界面。 几何分析引擎集成到系统中，用于提取作为可制造性规则输入所需的各种功能和相应参数。 该系统还涉及规则和分析引擎的可扩展接口，允许用户编写自己的定制规则和引擎，并将其集成到基于CAD的DFX评估系统中。

公开(公告)号：US20110093106A1

公开(公告)日：2011-04-21

申请号：US12797002

申请日：2010-06-09

申请人： Bhaskar Sinha ,  Ashish Patil ,  Ajay A. Deshpande ,  Alpana Sharma ,  Christine Zuzart ,  Sameer Kondejkar ,  Rajesh Jain ,  Nitin Umap ,  Rahul Rajadhyaksha

发明人： Bhaskar Sinha ,  Ashish Patil ,  Ajay A. Deshpande ,  Alpana Sharma ,  Christine Zuzart ,  Sameer Kondejkar ,  Rajesh Jain ,  Nitin Umap ,  Rahul Rajadhyaksha

IPC分类号： G06F19/00

CPC分类号： B29C45/7693 ,  G06F17/50 ,  G06F2217/41

摘要： A method of automatic manufacturability evaluation of plastic models comprises generation of a likely pulling direction, recognition of common features on plastic parts, and then applying manufacturability rules The manufacturability rules can be specified and customized through user specified rule parameters and depend upon the geometric parameters of the recognized features. A system comprises a user interface for selection and customization of DFX (Design for ‘X’) rules for evaluation of a design. The system includes a user interface integrated with a CAD system for receiving the CAD data and displaying the results to the user. Geometry analysis engines are integrated into the system, for extracting the various features and corresponding parameters required as input to the manufacturability rules. The system further involves extensible interfaces for rules and analysis engines which allows users to write their own customized rules and engines and integrate these into the CAD based DFX evaluation system.

摘要翻译： 塑料模型的自动制造性评估方法包括产生可能的拉动方向，识别塑料部件上的共同特征，然后应用可制造性规则可制造性规则可以通过用户指定的规则参数来指定和定制，并且取决于几何参数 公认的功能。 系统包括用于选择和定制DFX（用于'X'的设计）用于评估设计的规则的用户界面。 该系统包括与CAD系统集成的用于接收CAD数据并将结果显示给用户的用户界面。 几何分析引擎集成到系统中，用于提取作为可制造性规则输入所需的各种功能和相应参数。 该系统还涉及规则和分析引擎的可扩展接口，允许用户编写自己的定制规则和引擎，并将其集成到基于CAD的DFX评估系统中。

公开(公告)号：US5423013A

公开(公告)日：1995-06-06

申请号：US754810

申请日：1991-09-04

申请人： Richard I. Baum ,  Brent A. Carlson ,  Moon J. Kim ,  Michael G. Mall ,  Casper A. Scalzi ,  Bhaskar Sinha

发明人： Richard I. Baum ,  Brent A. Carlson ,  Moon J. Kim ,  Michael G. Mall ,  Casper A. Scalzi ,  Bhaskar Sinha

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F12/08

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F12/0623 ,  G06F9/32 ,  G06F2212/206

摘要： Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.

摘要翻译： 允许指令和数据位于数据处理系统的大尺寸实际存储器的多个部分中的任何一个或多个中。 任何存储器部分通过将传统的小实际/绝对地址与传统的小尺寸存储器使用的地址扩展器连接来定位。 中央处理器扩展地址模式（CPEAM）寄存器内容指示AR（s），ASTE，STE（s）或PTE的扩展器的位置，供中央处理器或I / O操作使用。 输入输出扩展地址模式（IOEAM）寄存器内容指示扩展器在ORB（s），CCW（s）或IDAW中的位置，供I / O操作使用。 如果不使用任何一个或两个，则兼容模式将CPEAM和IOEAM中的一个或两个设置为零。

公开(公告)号：US07313816B2

公开(公告)日：2007-12-25

申请号：US10022578

申请日：2001-12-17

申请人： Bhaskar Sinha ,  Ravigopal Vennelakanti ,  Goplnath Rebala

发明人： Bhaskar Sinha ,  Ravigopal Vennelakanti ,  Goplnath Rebala

IPC分类号： H04L9/32

CPC分类号： H04L63/0428 ,  H04L9/083 ,  H04L9/3213 ,  H04L63/062 ,  H04L63/0807 ,  H04L63/102

摘要： A system and method for authenticating a client having a privilege server, a head end server, and a web adapter performs the steps of negotiating an authentication scheme between the server proxy and the privilege server. User information is presented to the web adapter. The user information is provided to the head end server and in turn presents the information to the web adapter. The user is validated in accordance with the authentication scheme. When the user is validated a ticket is generated for the user. The ticket is presented to the client privilege server proxy that decrypts the ticket. A token is formed from the ticket and the client user identification. The token from the client is provided to the privilege server. A packet is formed having a sequence number and session key encrypted with the ticket. The packet is provided to the head end server which in turn authenticates the user. The packet is provided to the client privilege proxy which decrypts the packet and sends the ticket and the sequence number encrypted with the session key to the data server through the web adapter. User is validated at the data server and privileges are granted thereto.

摘要翻译： 用于认证具有特权服务器，头端服务器和web适配器的客户端的系统和方法执行在服务器代理和特权服务器之间协商认证方案的步骤。 用户信息被呈现给Web适配器。 将用户信息提供给头端服务器，并将信息呈现给web适配器。 用户根据认证方案进行验证。 当用户被验证时，为用户生成故障单。 将票证提交给解密票证的客户端特权服务器代理。 令牌是从票证和客户端用户标识形成的。 来自客户端的令牌被提供给特权服务器。 形成具有使用票证加密的序列号和会话密钥的分组。 该分组被提供给头端服务器，后端认证用户。 该分组被提供给客户端特权代理，该代理对数据包进行解密，并通过web适配器将会话密钥和用会话密钥加密的序列号发送到数据服务器。 用户在数据服务器上进行验证，并授予其权限。

公开(公告)号：US5706489A

公开(公告)日：1998-01-06

申请号：US544496

申请日：1995-10-18

申请人： Chi-Hung Chi ,  Hatem Mohamed Ghafir ,  Balakrishna Raghavendra Iyer ,  Inderpal Singh Narang ,  Gururaj Seshagiri Rao ,  Bhaskar Sinha

发明人： Chi-Hung Chi ,  Hatem Mohamed Ghafir ,  Balakrishna Raghavendra Iyer ,  Inderpal Singh Narang ,  Gururaj Seshagiri Rao ,  Bhaskar Sinha

IPC分类号： G06F9/38

CPC分类号： G06F9/30076 ,  G06F9/3863 ,  G06F9/3877

摘要： A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU do the rest of the operation synchronously, or c) resume the parallel operation in the processor or a hardware assist if an interruption caused the PIE-PF parallel operation to be checkpointed.

摘要翻译： 用于获得可以提供硬件辅助的频繁使用的编程操作（诸如数据库记录压缩或扩展，加密编码/解码，页面移动等）的并行指令执行（PIE）的方法。 这些功能可以与PIE处理设备（PIE-PF）的CPU处理并行执行。 该方法是基于硬件/微代码，并以监控模式使用软件控制。 优选实施例由操作系统下的特权子系统软件控制，并且不使用I / O通道定向的卸载处理。 当CPU在PIE-PF的不完全并行操作期间中断时，它将以子系统可访问的方式在主存储中进行检查。 子系统（完成目前的CPU操作，如数据库记录谓词评估）可以通过检查共享存储器中的控制块中的指示符来检查PIE-PF操作的完成情况，此外，如果并行操作未完成 CPU可以：a）与CPU中的其他处理并行执行PIE-PF处理，b）停止并行PIE-PF异步操作，并让CPU同步执行其余操作，或c）恢复并行 如果中断导致PIE-PF并行操作被检查点，则处理器中的操作或硬件辅助。

公开(公告)号：US5655146A

公开(公告)日：1997-08-05

申请号：US680069

申请日：1996-07-12

申请人： Richard Irwin Baum ,  Glen Alan Brent ,  Hatem Mohamed Ghafir ,  Balakrishna Raghavendra Iyer ,  Inderpal Singh Narang ,  Gururaj Seshagiri Rao ,  Casper Anthony Scalzi ,  Satya Prakash Sharma ,  Bhaskar Sinha ,  Lee Hardy Wilson

发明人： Richard Irwin Baum ,  Glen Alan Brent ,  Hatem Mohamed Ghafir ,  Balakrishna Raghavendra Iyer ,  Inderpal Singh Narang ,  Gururaj Seshagiri Rao ,  Casper Anthony Scalzi ,  Satya Prakash Sharma ,  Bhaskar Sinha ,  Lee Hardy Wilson

IPC分类号： G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F15/16 ,  G06F15/177 ,  G06F13/12

CPC分类号： G06F9/5055 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/5044 ,  G06F9/547 ,  G06F2209/509

摘要： A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity. Coexecutors can be of the same architecture or of a totally different architecture from the CPs to provide an efficient processing environment for the offloaded functions. The coexecutor interfaces host software which provides the requests to the coexecutor. Offloaded modules, once accessed by the coexecutor, may be cached in coexecutor local storage for use by future requests to allow subsequent invocations to proceed without waiting to again load the same module.

摘要翻译： 用于执行由数据处理系统中的中央处理器（CP）卸载的执行器，如由一个或多个执行控制程序请求的，其包括主机操作系统（主机OS）以及在主机OS下执行的子系统程序和应用程序。 卸载的功能体现在代码模块中。 代码模块在执行程序中执行，与CP执行的非卸载函数并行执行。 因此，CP不需要执行可由coexecutor执行的功能。 向请求者执行的CP请求在与控制程序相同的约束和访问限制下指定由主机共享存储器由coexecutor访问的代码模块。 共同执行者可以模拟主机动态地址转换，并且可以使用提供的主机存储密钥来访问主机存储。 coexecutor的受限访问操作状态维护数据完整性。 共同执行者可以是与CP相同的架构或与CP完全不同的架构，为卸载的功能提供有效的处理环境。 接口主机将向主机提供请求的主机软件。 卸载的模块一旦被coexecutor访问，就可以被缓存在coexecutor本地存储器中，供将来的请求使用，以允许后续的调用继续进行，而不用等待再次加载相同的模块。

公开(公告)号：US5426748A

公开(公告)日：1995-06-20

申请号：US816911

申请日：1992-01-03

申请人： James G. Brenza ,  Joseph M. Gdaniec ,  Peter H. Gum ,  Kathryn M. Jackson ,  Mark M. Maccabee ,  Casper A. Scalzi ,  Bhaskar Sinha

发明人： James G. Brenza ,  Joseph M. Gdaniec ,  Peter H. Gum ,  Kathryn M. Jackson ,  Mark M. Maccabee ,  Casper A. Scalzi ,  Bhaskar Sinha

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0292

摘要： An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage. The host LVA is translated in a number of different ways to a host LRA, depending on the type of guest providing the corresponding guest RA or LRA. The guest types include V=V, V=FC, V=FD and V=R guests, which is indicated in a guest control block (GCB).

摘要翻译： 在计算机系统内的访客/主机环境中使用大地址的寻址方法。 客人是操作系统，主机是一个管理程序。 每个访客都使用本文公开的手段将访客实际地址空间（客户RAS）映射到主机大型实际地址空间（主机LRAS）。 为此，每个客户RAS首先通过将每个客户机RAS分配给主机LVAS中的一个或多个连续的虚拟寻址单元来分配给主机大型虚拟地址空间（LVAS）的连续部分，每个单元具有2GB（ GB）尺寸。 主机LVAS由主机访问列表（AL）中的一系列条目（ALE）表示，其中每个ALE表示主机LVAS中的2GB虚拟寻址单元。 通过使用表示客户RA或LRA的主机大型虚拟地址（主机LVA）的高阶部分，在AL中选择ALE。 从客户RA生成主机LVA以获得主机主存储器中的客户地址。 主机LVA根据提供相应客户RA或LRA的客户端类型，以多种不同的方式被转换到主机LRA。 客人类型包括V = V，V = FC，V = FD和V = R客人，在客人控制块（GCB）中指示。

公开(公告)号：US5454086A

公开(公告)日：1995-09-26

申请号：US928937

申请日：1992-08-11

申请人： Alan I. Alpert ,  Carl E. Clark ,  Michel H. T. Hack ,  Casper A. Scalzi ,  Richard J. Schmalz, deceased ,  Bhaskar Sinha

发明人： Alan I. Alpert ,  Carl E. Clark ,  Michel H. T. Hack ,  Casper A. Scalzi ,  Richard J. Schmalz, deceased ,  Bhaskar Sinha

IPC分类号： G06F11/28 ,  G06F9/40 ,  G06F11/36 ,  G06F9/00 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F9/4425

摘要： Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction. One or more hooked programs may concurrently use the same analyzer program. As soon as execution by the analyzer program ends for a hook instruction, its assigned HWA is released for use by another hook instruction.

摘要翻译： 在分析程序与程序中的每个挂钩指令之间提供动态执行链接。 提供特殊类型的挂钩指令用于挂钩程序。 该链接使分析程序作为每个挂钩指令的连续不间断执行的一部分执行。 该链接使用硬件和/或内部代码访问挂钩控制区域，其提供在完成钩指令时调用分析器程序的执行所需的链接信息，并且在分析器程序完成之后继续执行挂钩程序 。 链接信息包括进入分析器程序的入口位置，并且还定位HWAs序列的第一挂钩工作区域（HWA），HWA被分配给每个当前挂钩指令。 所分配的HWA在当前挂钩指令之后的指令处在挂钩程序中存储返回点位置。 一个或多个挂钩程序可以同时使用相同的分析程序。 一旦分析程序的执行结束为​​一个挂接指令，其分配的HWA被释放供另一个钩子指令使用。

公开(公告)号：US5442350A

公开(公告)日：1995-08-15

申请号：US968631

申请日：1992-10-29

申请人： Balakrishna R. Iyer ,  Clark Kurtz ,  Kenneth E. Plambeck ,  Bhaskar Sinha

发明人： Balakrishna R. Iyer ,  Clark Kurtz ,  Kenneth E. Plambeck ,  Bhaskar Sinha

IPC分类号： G06F5/00 ,  G06F12/00 ,  G06F17/30 ,  G06T9/00 ,  H03M7/30 ,  H03M7/40

CPC分类号： G06F17/30595 ,  G06T9/005 ,  H03M7/3088

摘要： Ziv-Lempel-type compression and expansion using separate static compression and expansion dictionaries as opposed to a single adaptive dictionary. The static dictionaries make random access processes usable for short data records instead of only long sequential data streams. Degree of compression and compression performance are improved by allowance of multiple extension characters per node and multiple children, of the same parent, that have the same first extension character. Performance is further improved by searching for matches on children of a parent and detecting a last possible match by means of fields in the parent instead of by accessing the children. Expansion performance is improved by representing in an entry not only the extension character or characters of the entry but also those of some number of ancestors of the entry, thus avoiding accessing the ancestors.

摘要翻译： Ziv-Lempel型压缩和扩展使用单独的静态压缩和扩展字典而不是单个自适应字典。 静态字典使随机访问过程可用于短数据记录，而不仅仅是长连续的数据流。 通过允许具有相同第一扩展字符的同一父节点的每个节点和多个子节点允许多个扩展字符来提高压缩和压缩性能。 通过搜索父母的子项的匹配并通过父项中的字段检测最后可能的匹配来进一步提高性能，而不是访问子级。 通过在条目中不仅表示条目的扩展字符或字符，而且在条目的一些数量的祖先中表示扩展性能，从而避免访问祖先。

公开(公告)号：US5361356A

公开(公告)日：1994-11-01

申请号：US847521

申请日：1992-03-06

申请人： Carl E. Clark ,  Jeffrey A. Frey ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Bhaskar Sinha

发明人： Carl E. Clark ,  Jeffrey A. Frey ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Bhaskar Sinha

IPC分类号： G06F12/10 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/40

CPC分类号： G06F9/30054 ,  G06F9/30003 ,  G06F9/3851 ,  G06F9/468

摘要： A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space. The ALET indexes to a target subspace identifier in the access list, and then the associated virtual address locates the target instruction in the identified target address space. BSG instruction execution controls restrict the BSG branching only to an instruction in the subspace group.

摘要翻译： 子空间组（BSG）中的分支在问题状态（例如由应用程序）执行，用于在被称为子空间组的受限制的一组地址空间内的地址空间之间提供快速指令分支。 子空间组包含两种类型的地址空间：基本空间和任何数量的子空间。 子空间组设置在与每个可调度单元（DU）相关联的控制表中。 该DU控制表包含：基本空间的标识符，包含子空间组中所有子空间的标识符的访问列表的标识符，CPU控制是否被最后给予子空间或基本空间的指示符，以及 组中最后输入的子空间的标识符。 BSG指令具有定义包含目标虚拟地址的通用寄存器的操作数和包含定义目标地址空间的访问列表入口令牌（ALET）的关联访问寄存器。 ALET索引到访问列表中的目标子空间标识符，然后相关联的虚拟地址将目标指令定位在所识别的目标地址空间中。 BSG指令执行控制将BSG分支限制到子空间组中的指令。