摘要:
Ziv-Lempel-type compression and expansion using separate static compression and expansion dictionaries as opposed to a single adaptive dictionary. The static dictionaries make random access processes usable for short data records instead of only long sequential data streams. Degree of compression and compression performance are improved by allowance of multiple extension characters per node and multiple children, of the same parent, that have the same first extension character. Performance is further improved by searching for matches on children of a parent and detecting a last possible match by means of fields in the parent instead of by accessing the children. Expansion performance is improved by representing in an entry not only the extension character or characters of the entry but also those of some number of ancestors of the entry, thus avoiding accessing the ancestors.
摘要:
Describes novel methods for compressing data character strings into "storage optimized indices" (SOIs) and stores their adaptive Ziv Lempel (AZL) indices, called "evolution based indices" (EBIs), in fields in corresponding entries in a SOI dictionary. The method also compresses data using the SOI dictionary, which accesses the corresponding EBIs for representing the compressed data. The EBIs are put into storage, or transmitted to a receiving location. Greater data compression processing efficiency is obtained by using the SOI dictionary than is available using prior types of AZL dictionaries. The disclosure further describes methods for decompressing EBI indices into corresponding phrases at a receiving location using either a conventional AZL dictionary or a SOI dictionary after translating received EBIs into SOIs. Also described is a submethod for phrase length determination for use in the decompression process. Using this phrase length detection, received phrases are decompressed in their reverse character order through a buffer, or directly in a target storage area, or in a combination of the latter two techniques. The phrase length may be stored in corresponding dictionary entries to avoid a length tracing process in the invention.
摘要:
A method of transmitting compressed data using a Ziv-Lempel compression/expansion algorithm, using an adaptive Ziv-Lempel (AZL) dictionary modified to a mature state. The mature state is signaled by a time to freeze signal sent as a switch-over signal from a transmitting location to each receiving location. These signals freeze and synchronize the AZL dictionaries at both locations, and starts a translation of the frozen AZL dictionary to a static SZL dictionary--at least at the transmitting location. The SZL dictionary is then used to compress records being transmitted. An index translation process is generates translation information to allow the receiving locations to decompress SZL indices into original characters. The AZL-to-SZL dictionary translation process re-organizes the frozen AZL to an SZL dictionary. The SZL process is used until either the end of the inputted sequence, or a time to unfreeze signal is generated. An SZL to AZL switch-over signal is generated in response to the time to unfreeze signal, which in turn signals a switch over back to the AZL process and invokes the saved frozen AZL dictionary to be used to until mature to on the current input data stream at which time the AZL is frozen and a switch-over signal is provided and a new SZL is generated.
摘要:
A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results. An offset value of ALEs can be utilized to generate an effective ADEN and ALEN, which are utilized for the address translation of the LVA.
摘要:
A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space. The ALET indexes to a target subspace identifier in the access list, and then the associated virtual address locates the target instruction in the identified target address space. BSG instruction execution controls restrict the BSG branching only to an instruction in the subspace group.
摘要:
Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.
摘要:
A system and method for authenticating a client having a privilege server, a head end server, and a web adapter performs the steps of negotiating an authentication scheme between the server proxy and the privilege server. User information is presented to the web adapter. The user information is provided to the head end server and in turn presents the information to the web adapter. The user is validated in accordance with the authentication scheme. When the user is validated a ticket is generated for the user. The ticket is presented to the client privilege server proxy that decrypts the ticket. A token is formed from the ticket and the client user identification. The token from the client is provided to the privilege server. A packet is formed having a sequence number and session key encrypted with the ticket. The packet is provided to the head end server which in turn authenticates the user. The packet is provided to the client privilege proxy which decrypts the packet and sends the ticket and the sequence number encrypted with the session key to the data server through the web adapter. User is validated at the data server and privileges are granted thereto.
摘要:
A method of automatic manufacturability evaluation of plastic models comprises generation of a likely pulling direction, recognition of common features on plastic parts, and then applying manufacturability rules The manufacturability rules can be specified and customized through user specified rule parameters and depend upon the geometric parameters of the recognized features. A system comprises a user interface for selection and customization of DFX (Design for ‘X’) rules for evaluation of a design. The system includes a user interface integrated with a CAD system for receiving the CAD data and displaying the results to the user. Geometry analysis engines are integrated into the system, for extracting the various features and corresponding parameters required as input to the manufacturability rules. The system further involves extensible interfaces for rules and analysis engines which allows users to write their own customized rules and engines and integrate these into the CAD based DFX evaluation system.
摘要:
A method of automatic manufacturability evaluation of plastic models comprises generation of a likely pulling direction, recognition of common features on plastic parts, and then applying manufacturability rules The manufacturability rules can be specified and customized through user specified rule parameters and depend upon the geometric parameters of the recognized features. A system comprises a user interface for selection and customization of DFX (Design for ‘X’) rules for evaluation of a design. The system includes a user interface integrated with a CAD system for receiving the CAD data and displaying the results to the user. Geometry analysis engines are integrated into the system, for extracting the various features and corresponding parameters required as input to the manufacturability rules. The system further involves extensible interfaces for rules and analysis engines which allows users to write their own customized rules and engines and integrate these into the CAD based DFX evaluation system.
摘要:
A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU do the rest of the operation synchronously, or c) resume the parallel operation in the processor or a hardware assist if an interruption caused the PIE-PF parallel operation to be checkpointed.