公开(公告)号：US20060277511A1

公开(公告)日：2006-12-07

申请号：US11142709

申请日：2005-06-01

申请人： Bhavna Agrawal ,  Peter Feldmann ,  Sani Nassif ,  Tomasz Nowicki ,  Grzegorz Swirszcz

发明人： Bhavna Agrawal ,  Peter Feldmann ,  Sani Nassif ,  Tomasz Nowicki ,  Grzegorz Swirszcz

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.

摘要翻译： 用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。 在存储元件的状态空间中计算安全区域，其表示稳定状态。 执行瞬态分析以确定到达安全区域之一所需的路径和时间。 基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

公开(公告)号：US20110154280A1

公开(公告)日：2011-06-23

申请号：US12640129

申请日：2009-12-17

申请人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

发明人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G06F2217/12 ,  Y02P90/265

摘要： An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

摘要翻译： 提供了一种计算与硬件设计布局中包括的多个形状相对应的电延迟范围的方法。 电延迟范围被转换成每个形状的形状公差。 使用形状公差产生硬件设计布局的光刻掩模，使得所生成的掩模中的形状的图像位于对应于相应形状的形状公差内。

公开(公告)号：US20070220455A1

公开(公告)日：2007-09-20

申请号：US11375477

申请日：2006-03-14

申请人： Rajiv Joshi ,  Rouwaida Kanj ,  Sani Nassif

发明人： Rajiv Joshi ,  Rouwaida Kanj ,  Sani Nassif

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G11C29/028 ,  G11C29/54 ,  G11C29/56004 ,  G11C29/56008 ,  G11C2029/0403

摘要： A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

摘要翻译： 用于在单元阵列中有效的单元故障率估计的方法和计算机程序提供了一种有效的机制，用于提高存储器阵列的性能超过现有水平/产量。 在单元电路参数之间执行初始搜索以确定关于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样，并且当已经累积了足够的故障点时，从检测到的故障点的平均值中选择一个平均值。 然后执行混合重要性采样（MIS）以有效地估计单个故障区域。 对于多个故障区域，通过沿随机矢量集改变存储器电路单元参数直到检测到故障来选择特定故障区域，从而将感兴趣的故障区域的边界识别为最接近的故障区域。 根据检测到的边界的位置，为MIS选择新的平均值。

公开(公告)号：US08281263B2

公开(公告)日：2012-10-02

申请号：US12640129

申请日：2009-12-17

申请人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

发明人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G03F1/70 ,  G06F2217/12 ,  Y02P90/265

摘要： An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

摘要翻译： 提供了一种计算与硬件设计布局中包括的多个形状对应的电延迟范围的方法。 电延迟范围被转换成每个形状的形状公差。 使用形状公差产生硬件设计布局的光刻掩模，使得所生成的掩模中的形状的图像位于对应于相应形状的形状公差内。

公开(公告)号：US20060265189A1

公开(公告)日：2006-11-23

申请号：US11460591

申请日：2006-07-27

申请人： Sani Nassif

发明人： Sani Nassif

IPC分类号： G21C17/00

CPC分类号： G01R31/31718 ,  G01R31/318511 ,  G01R31/318533

摘要： A circuit for computing moment pre-products for statistical analysis provides reduced data transfer volume for on-chip statistical measurements. The circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from a wafer without losing information valuable to the analysis. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. The circuit can use look-up tables and adder/accumulators to accumulate the contributions of each measurement to each exponentiation, or use a multiplier arrangement to determine the contributions. The multipliers can be implemented in the adder/accumulators by clocking the adder/accumulators by corresponding counts determined from the measurement data and lower-order exponentiations. Ranges of the measurement values are determined by capturing maximum and minimum values using comparators as the measurements are input.

摘要翻译： 用于计算用于统计分析的时间产品的电路为片上统计测量提供了减少的数据传输量。 该电路计算一个或多个测量电路的输出的多个指数的和，从而减少必须从晶片传输的数据量，而不会丢失对分析有价值的信息。 输入数据的整数缩放被布置在零和单位之间，使得指数都类似地在零和单位之间。 电路可以使用查找表和加法器/累加器来将每个测量的贡献累积到每个乘幂，或者使用乘数布置来确定贡献。 乘法器可以通过对加法器/累加器进行计时，通过从测量数据和低阶指数确定的相应计数来在加法器/累加器中实现。 通过在输入测量值时通过比较器捕获最大值和最小值来确定测量值的范围。

公开(公告)号：US20060235647A1

公开(公告)日：2006-10-19

申请号：US11109092

申请日：2005-04-19

申请人： Sani Nassif

发明人： Sani Nassif

IPC分类号： G06F15/00

CPC分类号： G01R31/31718 ,  G01R31/318511 ,  G01R31/318533

摘要： An on-wafer method and apparatus for pre-processing measurements of process and environment-dependent circuit performance variables improves yield/performance test and analysis throughput. An on-wafer circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from the wafer without losing information valuable to the analysis. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. The circuit can use look-up tables and adder/accumulators to accumulate the contributions of each measurement to each exponentiation, or use a multiplier arrangement to determine the contributions. The multipliers can be implemented in the adder/accumulators by clocking the adder/accumulators by corresponding counts determined from the measurement data and lower-order exponentiations. Ranges of the measurement values are determined by capturing maximum and minimum values using comparators as the measurements are input.

摘要翻译： 用于预处理过程和环境相关电路性能变量测量的晶圆方法和装置提高了产量/性能测试和分析产量。 晶片间电路计算一个或多个测量电路的输出的多个乘积的和，从而减少必须从晶片传送的数据量，而不会丢失对分析有价值的信息。 输入数据的整数缩放被布置在零和单位之间，使得指数都类似地在零和单位之间。 电路可以使用查找表和加法器/累加器来将每个测量的贡献累积到每个乘幂，或者使用乘数布置来确定贡献。 乘法器可以通过对加法器/累加器进行计时，通过从测量数据和低阶指数确定的相应计数来在加法器/累加器中实现。 通过在输入测量值时通过比较器捕获最大值和最小值来确定测量值的范围。

公开(公告)号：US20050044515A1

公开(公告)日：2005-02-24

申请号：US10646425

申请日：2003-08-22

申请人： Emrah Acar ,  Anirudh Devgan ,  Sani Nassif

发明人： Emrah Acar ,  Anirudh Devgan ,  Sani Nassif

IPC分类号： G06F17/50 ,  G06F9/45 ,  H01L21/82

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/78

摘要： An integrated circuit design has circuit macros made up of device cells. The cells are characterized by determining the leakage current dependency on various process, environmental and voltage parameters. When circuit macros are designed their leakage power is calculated using this data and multi-dimensional models for power and temperature distribution. Circuit macros are identified as timing-critical and timing-noncritical macros. Statistical methods are used to determine the average leakage sensitivities for the specific circuit macros designed. The designer uses the sensitivity data to determine how to redesign selected circuit macros to reduce leakage power. Reducing leakage power in these selected circuits may be used to reduce overall IC power or the improved power margins may be used in timing-critical circuits to increase performance while keeping power dissipation unchanged.

摘要翻译： 集成电路设计具有由器件单元组成的电路宏。 电池的特征在于确定泄漏电流对各种工艺，环境和电压参数的依赖性。 当设计电路宏时，使用该数据和功率和温度分布的多维模型计算其漏电功率。 电路宏被标识为时序关键和时序非关键宏。 统计方法用于确定设计的特定电路宏的平均泄漏灵敏度。 设计师使用灵敏度数据来确定如何重新设计选定的电路宏以减少漏电功率。 降低这些选择的电路中的漏电功率可以用于降低总体IC功率，或者可以在时序关键电路中使用改进的功率余量来提高性能，同时保持功率消耗不变。