公开(公告)号：US08281263B2

公开(公告)日：2012-10-02

申请号：US12640129

申请日：2009-12-17

申请人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

发明人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G03F1/70 ,  G06F2217/12 ,  Y02P90/265

摘要： An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

摘要翻译： 提供了一种计算与硬件设计布局中包括的多个形状对应的电延迟范围的方法。 电延迟范围被转换成每个形状的形状公差。 使用形状公差产生硬件设计布局的光刻掩模，使得所生成的掩模中的形状的图像位于对应于相应形状的形状公差内。

公开(公告)号：US20110154280A1

公开(公告)日：2011-06-23

申请号：US12640129

申请日：2009-12-17

申请人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

发明人： Kanak Agarwal ,  Shayak Banerjee ,  Sani Nassif ,  Chin Ngai Sze

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G06F2217/12 ,  Y02P90/265

摘要： An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

摘要翻译： 提供了一种计算与硬件设计布局中包括的多个形状相对应的电延迟范围的方法。 电延迟范围被转换成每个形状的形状公差。 使用形状公差产生硬件设计布局的光刻掩模，使得所生成的掩模中的形状的图像位于对应于相应形状的形状公差内。

公开(公告)号：US20070216457A1

公开(公告)日：2007-09-20

申请号：US11377507

申请日：2006-03-16

申请人： Kanak Agarwal ,  Robert Montoye

发明人： Kanak Agarwal ,  Robert Montoye

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： Methods and arrangements to adjust a duty cycle of a clock signal are disclosed. Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

摘要翻译： 公开了调整时钟信号占空比的方法和装置。 实施例可以包括占空比控制器，用于基于延迟信号和输入时钟信号来调整时钟信号的占空比。 占空比检测器可以基于输出信号的占空比来确定具有频率的信号，并且校正模块可以比较检测器信号的频率以产生延迟信号。 在一些实施例中，一旦输出时钟信号的占空比达到期望的占空比（例如百分之五十），则校正模块可以被关断。

公开(公告)号：US20070200593A1

公开(公告)日：2007-08-30

申请号：US11301728

申请日：2005-12-13

申请人： Kanak Agarwal ,  Damir Jamsek ,  Kevin Nowka

发明人： Kanak Agarwal ,  Damir Jamsek ,  Kevin Nowka

IPC分类号： H03K19/173

CPC分类号： H03K19/0016

摘要： A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation for process variation. A set of processing blocks having a power supply selectable from two different power supply voltage levels is provided. The power level of the overall circuit is set by selecting the power supply voltage for each block to yield a combination of blocks that meets operating requirements. Alternatively, one circuit per pair from a set of pairs of redundant logic blocks supplied by the different power supply voltage levels can be selected to meet the operating requirements. The unselected blocks can be disabled by disabling foot devices or disabling transitions at the inputs to the unselected blocks. Performance measurement and feedback circuits can be included to tune the power consumption and performance level of the circuit to meet an expected level.

摘要翻译： 具有通过每块可选工作电压电平的动态功率和性能控制的数字电路允许动态定制工作电源以处理需求和/或对工艺变化的补偿。 提供了具有可从两个不同电源电压电平选择的电源的一组处理块。 通过选择每个块的电源电压来设置整个电路的功率电平，以产生满足运行要求的块组合。 或者，可以选择由不同电源电压电平提供的一组冗余逻辑块中的每对一个电路以满足操作要求。 可以通过禁用脚装置或禁用未选择块的输入上的转换来禁用未选择的块。 可以包括性能测量和反馈电路来调整电路的功耗和性能水平以达到预期的水平。

公开(公告)号：US07966535B2

公开(公告)日：2011-06-21

申请号：US12391085

申请日：2009-02-23

申请人： Kanak Agarwal

发明人： Kanak Agarwal

IPC分类号： G01R31/28

CPC分类号： G01R31/31719 ,  G01R31/318536 ,  G11C29/32 ,  G11C2029/3202

摘要： A circuit configuration for testing integrated circuitry featuring a number of system scan flip flops wired in series and connected to the integrated circuitry for inputting test signals and receiving test data back. At the front and back ends of the system scan flip flops there is an input multiplexer and an output multiplexer, each with a control input tied to a comparator. The multiplexers isolate the test circuitry until a predetermined scan key is received. When the comparator receives a k-bit scan key it enables the multiplexer to pass test data to the system scan flip flops.

摘要翻译： 用于测试集成电路的电路配置，其特征在于具有串联布线的多个系统扫描触发器，并连接到用于输入测试信号和接收测试数据的集成电路。 在系统扫描触发器的前端和后端，有一个输入多路复用器和一个输出多路复用器，每个都有一个与比较器相连的控制输入。 多路复用器隔离测试电路，直到接收到预定的扫描键。 当比较器接收到k位扫描键时，它使多路复用器将测试数据传送到系统扫描触发器。

公开(公告)号：US20100218054A1

公开(公告)日：2010-08-26

申请号：US12391085

申请日：2009-02-23

申请人： Kanak Agarwal

发明人： Kanak Agarwal

IPC分类号： G11C29/08 ,  G06F11/26

CPC分类号： G01R31/31719 ,  G01R31/318536 ,  G11C29/32 ,  G11C2029/3202

摘要： A circuit configuration for testing integrated circuitry featuring a number of system scan flip flops wired in series and connected to the integrated circuitry for inputting test signals and receiving test data back. At the front and back ends of the system scan flip flops there is an input multiplexer and an output multiplexer, each with a control input tied to a comparator. The multiplexers isolate the test circuitry until a predetermined scan key is received. When the comparator receives a k-bit scan key it enables the multiplexer to pass test data to the system scan flip flops.

摘要翻译： 用于测试集成电路的电路配置，其特征在于具有串联布线的多个系统扫描触发器，并连接到用于输入测试信号和接收测试数据的集成电路。 在系统扫描触发器的前端和后端，有一个输入多路复用器和一个输出多路复用器，每个都有一个与比较器相连的控制输入。 多路复用器隔离测试电路，直到接收到预定的扫描键。 当比较器接收到k位扫描键时，它使多路复用器将测试数据传送到系统扫描触发器。