公开(公告)号：US5539216A

公开(公告)日：1996-07-23

申请号：US329925

申请日：1994-10-27

申请人： Bich-Yen Nguyen ,  Marius Orlowski ,  Philip J. Tobin ,  Jim Hayden ,  Jack Higman

发明人： Bich-Yen Nguyen ,  Marius Orlowski ,  Philip J. Tobin ,  Jim Hayden ,  Jack Higman

IPC分类号： H01L27/11 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/78696 ,  H01L27/1108 ,  Y10S257/915

摘要： A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

摘要翻译： 单片半导体本体（26）位于形成在绝缘层（14）中的开口（16）中。 单片半导体本体（26）包括填充绝缘层（14）中的开口（16）并接触半导体区域（12）的细长区域（20）。 单片半导体本体（26）还包括覆盖细长区域（20）的表面区域（24）和邻近开口（16）的绝缘层（14）的表面（22）的一部分。 通过首先将半导体材料层沉积到开口（16）中，然后平坦化绝缘层（14）的表面来制造单片半导体本体（26）。 接下来，进行选择性沉积工艺以使用开口（16）中的半导体材料形成表面区域（24）作为成核位置。 表面区域（24）的曲率半径由选择性沉积过程中受控过度生长的量决定。

公开(公告)号：US5422504A

公开(公告)日：1995-06-06

申请号：US235994

申请日：1994-05-02

申请人： Kuo-Tung Chang ,  Umesh Sharma ,  Jack Higman

发明人： Kuo-Tung Chang ,  Umesh Sharma ,  Jack Higman

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L29/42324 ,  H01L29/42328

摘要： An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (22) from the source region (12). The control gate electrode (20) overlies a third channel region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

摘要翻译： EEPROM存储器阵列包括具有形成为与控制栅极（20）相邻的侧壁间隔的浮栅电极（22）的多个存储单元。 源极和漏极区域（12,14）驻留在半导体衬底（10）中并且在它们之间限定分割的沟道区域（16）。 选择栅极（18）覆盖在第一沟道区（24）上，并将浮栅电极（22）与源极区（12）分离。 控制栅电极（20）覆盖第三沟道区（28），并将浮栅电极（22）与漏区（14）分离。 浮栅电极（22）覆盖第二沟道区（26），并由薄隧道氧化物层（42）分离。 本发明的EEPROM装置可以通过源侧注入或通过Fowler-Nordheim隧道进行编程。 此外，提供了一种制造使用相邻的选择栅电极（18,18'）作为掺杂掩模的EEPROM阵列的工艺。

公开(公告)号：US5494838A

公开(公告)日：1996-02-27

申请号：US448096

申请日：1995-05-23

申请人： Kuo-Tung Chang ,  Umesh Sharma ,  Jack Higman

发明人： Kuo-Tung Chang ,  Umesh Sharma ,  Jack Higman

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L27/115 ,  H01L29/42324 ,  H01L29/42328

摘要： An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

摘要翻译： EEPROM存储器阵列包括具有形成为与控制栅极（20）相邻的侧壁间隔的浮栅电极（22）的多个存储单元。 源极和漏极区域（12,14）驻留在半导体衬底（10）中并且在它们之间限定分割的沟道区域（16）。 选择栅电极（18）覆盖在第一沟道区（24）上，并将浮栅电极（2）与源极区（12）分离。 控制栅电极（20）覆盖第三通道区域（28），并将浮栅电极（22）与漏极区域（14）分离。 浮栅电极（22）覆盖第二沟道区（26），并由薄隧道氧化物层（42）分离。 本发明的EEPROM装置可以通过源侧注入或通过Fowler-Nordheim隧道进行编程。 此外，提供了一种制造使用相邻的选择栅电极（18,18'）作为掺杂掩模的EEPROM阵列的工艺。

公开(公告)号：US20070220388A1

公开(公告)日：2007-09-20

申请号：US11366286

申请日：2006-03-02

申请人： Qadeer Quereshi ,  James Burnett ,  Jack Higman ,  Thomas Jew

发明人： Qadeer Quereshi ,  James Burnett ,  Jack Higman ,  Thomas Jew

IPC分类号： G01R31/28

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

摘要翻译： 一种用于调整具有存储器和逻辑的集成电路的操作参数的方法，其中所述逻辑包括定时电路，包括访问所述存储器，确定所述存储器访问相对于所述定时电路的速度的相对速度，以及选择性地 根据相对速度调整运行参数。 在一个实施例中，集成电路可以包括环形振荡器，具有耦合到环形振荡器的输出的时钟输入的移位寄存器以及耦合到移位寄存器的输出的比较逻辑。 响应于启动对存储器的存储器访问而响应于完成存储器访问而禁用移位寄存器。 比较逻辑提供表示存储器的相对速度的相对速度指示符。

公开(公告)号：US20070171713A1

公开(公告)日：2007-07-26

申请号：US11337775

申请日：2006-01-23

申请人： Bradford Hunter ,  James Burnett ,  Jack Higman

发明人： Bradford Hunter ,  James Burnett ,  Jack Higman

IPC分类号： G11C16/04

CPC分类号： G11C11/412 ,  G11C11/413

摘要： An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage. This bi-directional low voltage drop low loss switch can increase the write margin of the memory cell wherein the high impedance read port can provide increased isolation for the stored value during the read phase increasing the performance of the memory cell.

摘要翻译： 电子设备包括存储单元，其利用双向低阻抗低压降全通栅极在写入阶段期间将位单元连接到位写入线，并且在读取阶段期间，全通道栅极可以保持关断，并且 高输入阻抗读取端口可以获取和传输存储器单元存储的逻辑状态到另一个子系统。 可以通过与NMOS器件并联连接P型金属半导体场效应晶体管（PMOS）并用差分信号驱动晶体管的栅极来实现全通栅。 当写入操作需要电流沿第一方向流动时，PMOS器件提供可忽略的电压降，并且当写操作需要电流在第二或相反方向上流动时，NMOS器件可以提供可忽略的电压。 该双向低压降低损耗开关可以增加存储单元的写入裕度，其中高阻抗读取端口可以在读取阶段期间为存储的值提供增加的隔离以增加存储单元的性能。