公开(公告)号：US5648985A

公开(公告)日：1997-07-15

申请号：US348359

申请日：1994-11-30

申请人： Bjorn E. Bjerede ,  Joseph T. Lipowski ,  Benny Madsen ,  Sheldon L. Gilbert ,  James E. Petranovich

发明人： Bjorn E. Bjerede ,  Joseph T. Lipowski ,  Benny Madsen ,  Sheldon L. Gilbert ,  James E. Petranovich

IPC分类号： H04L27/10 ,  H04B1/26 ,  H04B1/40 ,  H04B1/56 ,  H04J1/00 ,  H04L5/14 ,  H04L27/00 ,  H04L27/18 ,  H04B1/38

CPC分类号： H04L27/0008 ,  H04B1/403 ,  H04L5/143 ,  H04L5/1492 ,  H04B1/56

摘要： An integrated circuit chip set is provided for use in a radio communication system in which a modulated digital input signal is processed for transmission and a modulated signal received from an antenna is processed to provide an output signal, wherein the modulation of the signals is either QPSK or FSK and the signal transmission and reception is by either TDD or FDD. The chip set includes an IF integrated circuit chip for processing a digital input signal to convert the digital input signal into an analog input signal and to provide the input signal at an intermediate frequency and for processing a received signal at the intermediate frequency to down convert the frequency thereof and to provide an output signal from the down-converted received signal; and an RF integrated circuit chip for processing the input signal provided by the IF chip at the intermediate frequency to up convert the frequency thereof to a transmission frequency and for processing a received signal provided at the reception frequency to down convert the frequency thereof to the intermediate frequency. The IF chip includes switches and terminals for enabling the IF chip to be connected for processing by the IF chip of QPSK-modulated signals or to be connected for processing by the IF chip of FSK-modulated signals; and the RF chip includes terminals for enabling the RF chip to be connected for processing by the RF chip of TDD transmitted and received signals or to be connected for processing by the RF chip of FDD transmitted and received signals.

摘要翻译： 提供一种用于无线电通信系统的集成电路芯片组，其中调制的数字输入信号被处理用于传输，并且处理从天线接收的调制信号以提供输出信号，其中信号的调制是QPSK 或FSK，并且信号发送和接收是通过TDD或FDD。 芯片组包括用于处理数字输入信号以将数字输入信号转换成模拟输入信号并且以中频提供输入信号并用于处理中频处的接收信号的IF集成电路芯片， 并提供来自下变频接收信号的输出信号; 以及用于处理由IF芯片在中频提供的输入信号的RF集成电路芯片，以将其频率向上转换为传输频率，并处理以接收频率提供的接收信号，以将其频率下变频到中间 频率。 IF芯片包括用于使IF芯片连接以由IF芯片进行QPSK调制信号处理的开关和端子，或者被IFK芯片进行FSK调制信号的处理连接; 并且RF芯片包括终端，用于使RF芯片能够被连接用于RF芯片的TDD发送和接收信号的处理，或者被连接以供FDD发送和接收信号的RF芯片处理。

公开(公告)号：US5722040A

公开(公告)日：1998-02-24

申请号：US13625

申请日：1993-02-04

申请人： Bjorn E. Bjerede ,  Joseph T. Lipowski ,  James E. Petranovich ,  F. Matthew Rhodes

发明人： Bjorn E. Bjerede ,  Joseph T. Lipowski ,  James E. Petranovich ,  F. Matthew Rhodes

IPC分类号： H03J1/00 ,  H04B1/40 ,  H04B7/26

CPC分类号： H04B1/405 ,  H03J1/0008

摘要： Methods and apparatus for digital cordless telephone systems are preferably implemented in an integrated circuit chip set having one or more chips, adapted to receive a voice signal, for converting the voice signal into a digital signal of a desired form, for converting the digital signal into an analog signal and for modifying the frequency of the analog signal, for up converting during transmission the frequency of the analog signal from an intermediate frequency to a desired radio frequency and for down converting during reception from a selected radio frequency to the intermediate frequency and for amplifying the radio frequency signal during transmission and for switching the antenna between the transmit and receive paths. It is preferred for the chip set to include a base chip, an intermediate frequency chip, a radio frequency chip and an amplifier chip. It is preferred to also provide a synthesizer integrated circuit chip for generating carrier select signals to be used by the radio frequency chip in selecting desired carrier frequencies. The invention also includes a frequency translation scheme to be utilized in conjunction with the various chips. Utilization of this scheme serves to reduce spurious noise as well as to suppress transmit signals during receive operations. The invention also includes various sensors for adjusting the level of the signal to be transmitted and for adjusting the level of the signal received at the antenna.

摘要翻译： 用于数字无绳电话系统的方法和装置优选地在具有一个或多个芯片的集成电路芯片组中实现，该芯片组适于接收语音信号，用于将语音信号转换成所需形式的数字信号，以将数字信号转换成 模拟信号，用于修改模拟信号的频率，用于在将模拟信号的频率从中频到期望的射频传输期间进行上转换，并且用于在从选定的射频到中频的接收期间进行下变频， 在传输期间放大射频信号，并在发射和接收路径之间切换天线。 芯片组优选包括基片，中频芯片，射频芯片和放大器芯片。 优选地还提供一种用于产生载波选择信号的合成器集成电路芯片，以在射频芯片选择期望的载波频率时使用。 本发明还包括与各种芯片结合使用的频率转换方案。 该方案的利用有助于减少杂散噪声以及在接收操作期间抑制发射信号。 本发明还包括用于调整要发送的信号的电平并用于调整在天线处接收的信号的电平的各种传感器。

公开(公告)号：US5526527A

公开(公告)日：1996-06-11

申请号：US131210

申请日：1993-10-01

申请人： Joseph T. Lipowski ,  Bjorn E. Bjerede ,  John F. O'Connor

发明人： Joseph T. Lipowski ,  Bjorn E. Bjerede ,  John F. O'Connor

IPC分类号： H03L7/087 ,  H03L7/193 ,  H04B1/40 ,  H04M1/725 ,  H04Q7/32 ,  H03L7/00

CPC分类号： H03L7/087 ,  H03L7/193 ,  H04B1/405 ,  H04M1/72502

摘要： Methods and apparatus for frequency synthesization are shown for generating an output signal of desired frequency. The frequency synthesizer includes an oscillator for generating an output signal at the desired frequency in response to a control signal. A first detector compares the output signal to a reference signal and generates a first difference signal representative of the differences, preferably in phase and frequency, between the output and the reference signals. A second detector compares the output signal to the reference signal and generates a second difference signal. A controller generates the control signal in response to either the first or second difference signal. A selector member selects between the first and second detectors to provide either the first or second control signal to the controller in response to a selection signal. A lock detector detects when the output signal and said reference signal are in a predetermined relation and generates the switch signal in response to the detection of the occurrence of such predetermined relation.

摘要翻译： 示出用于产生所需频率的输出信号的用于频率合成的方法和装置。 频率合成器包括用于响应于控制信号产生期望频率的输出信号的振荡器。 第一检测器将输出信号与参考信号进行比较，并产生表示输出和参考信号之间的差异，优选地在相位和频率上的第一差分信号。 第二检测器将输出信号与参考信号进行比较，并产生第二差分信号。 控制器响应于第一或第二差信号产生控制信号。 选择器构件在第一和第二检测器之间选择以响应于选择信号向控制器提供第一或第二控制信号。 锁定检测器检测输出信号和所述参考信号何时处于预定关系，并且响应于检测到这种预定关系的发生而产生开关信号。

公开(公告)号：US5073869A

公开(公告)日：1991-12-17

申请号：US398735

申请日：1989-08-25

申请人： Bjorn E. Bjerede

发明人： Bjorn E. Bjerede

IPC分类号： H03L7/00 ,  G06F1/02 ,  H03J3/00

CPC分类号： G06F1/022 ,  G06F2211/902

摘要： A direct digital frequency synthesizer generates an analog waveform of a predetermined frequency from accumulated digital frequency words which, as accumulated, represent the phase of a sine wave of the predetermined frequency. The synthesizer includes a phase accumulator, a 4-bit non-linear digital-to-analog converter (DAC) and a sample and hold circuit. The phase accumulator includes a 4-bit coarse-component accumulator for accumulating coarse phase components of the digital frequency words and a fine-component accumulator for accumulating fine phase components of the digital frequency words. The phase accumulator increments the coarse-component accumulator in response to the accumulated fine phase components exceeding a predetermined value. The 4-bit non-linear DAC converts the four bits accumulated in the coarse-component accumulator into an analog waveform of the predetermined frequency. The phase accumulator suppresses the generation of spurious frequency components in the analog waveform by randomly dithering the rate at which the coarse component accumulator is incremented by the phase accumulator. The sample and hold circuit is coupled to the output of the nonlinear DAC for mitigating any glitch errors induced in the nonlinear DAC by sampling the analog waveform at such times as when glitch-induced errors are not present.

公开(公告)号：US3946323A

公开(公告)日：1976-03-23

申请号：US491731

申请日：1974-07-25

申请人： Bjorn E. Bjerede

发明人： Bjorn E. Bjerede

IPC分类号： G01S1/44 ,  H03K5/1536 ,  H03L7/00 ,  H04L7/033 ,  H03K1/17 ,  H03B3/04 ,  H03K5/13

CPC分类号： G01S1/44 ,  H03K5/1536 ,  H03L7/00 ,  H04L7/0334

摘要： A digital phase locked loop circuit for use in synchronizing output timing pulses with the positive going zero-crossings of an input data signal by quantitizing the input analog data signal as digital information, storing the digital information at given times by timing pulses, pre-programming a counter with a count corresponding to the quantitized digital information stored, and advancing or lagging an updated timing pulse in accordance with the timed count of the program counter which count is synchronized with the zero-crossings of the input data signal, whereby the updated timing pulses move to synchronism with the zero-crossings of the input data signal.

摘要翻译： 数字锁相环电路，用于将输入定时脉冲与输入数据信号的正向过零点同步，将输入的模拟数据信号定量为数字信息，通过定时脉冲在预定时间存储数字信息，预编程 具有对应于存储的量化数字信息的计数的计数器，并且根据计数与输入数据信号的过零点同步的程序计数器的定时计数推进或滞后更新的定时脉冲，由此更新的定时 脉冲移动到与输入数据信号的过零点同步。