公开(公告)号：US08652910B2

公开(公告)日：2014-02-18

申请号：US13438250

申请日：2012-04-03

申请人： Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon ,  Il-Young Yoon

发明人： Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon ,  Il-Young Yoon

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.

摘要翻译： 在制造半导体器件的方法中，可以提供一种基板，其包括：底座，从基座的上表面突出并与基座一体形成的活动翅片，以及形成在活动件上的缓冲氧化膜图案 翅片与活动翅片接触。 可以在衬底上形成第一伪栅极膜以覆盖缓冲氧化膜图案，并且可以平滑第一伪栅极膜以暴露缓冲氧化膜图案。 可以在暴露的缓冲氧化膜图案和第一伪栅极膜上形成第二伪栅极膜。

公开(公告)号：US20120315732A1

公开(公告)日：2012-12-13

申请号：US13438250

申请日：2012-04-03

申请人： Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon ,  Il-Young Yoon

发明人： Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon ,  Il-Young Yoon

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L21/823431 ,  H01L21/845

摘要： In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.

摘要翻译： 在制造半导体器件的方法中，可以提供一种基板，其包括：底座，从基座的上表面突出并与基座一体形成的活动翅片，以及形成在活动件上的缓冲氧化膜图案 翅片与活动翅片接触。 可以在衬底上形成第一伪栅极膜以覆盖缓冲氧化膜图案，并且可以平滑第一伪栅极膜以暴露缓冲氧化膜图案。 可以在暴露的缓冲氧化膜图案和第一伪栅极膜上形成第二伪栅极膜。

公开(公告)号：US08399327B2

公开(公告)日：2013-03-19

申请号：US13240560

申请日：2011-09-22

申请人： Jong-Won Lee ,  Jae-Seok Kim ,  Bo-Un Yoon

发明人： Jong-Won Lee ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

摘要翻译： 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。

公开(公告)号：US20120122283A1

公开(公告)日：2012-05-17

申请号：US13240560

申请日：2011-09-22

申请人： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

发明人： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

摘要翻译： 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。

公开(公告)号：US08470663B2

公开(公告)日：2013-06-25

申请号：US13048683

申请日：2011-03-15

申请人： Seong-Kyu Yun ,  Jae-Seok Kim

发明人： Seong-Kyu Yun ,  Jae-Seok Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/544 ,  H01L29/7848 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.

摘要翻译： 制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。 在集成结构上形成第一初步绝缘中间层。 执行第一初步绝缘中间层的第一次抛光，直到暴露硬掩模图案的至少一个上表面，以形成第二预绝缘中间层。 蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出，以形成第三初步绝缘中间层。 执行硬掩模图案和第三预备绝缘中间层的第二次抛光，直到多晶硅图案暴露以形成绝缘中间层。 去除多晶硅图形以形成开口。 金属材料被放弃以在开口中形成栅极电极图案。

公开(公告)号：US08437260B2

公开(公告)日：2013-05-07

申请号：US12397876

申请日：2009-03-04

申请人： Ji-Ho Kim ,  Jae-Do Roh ,  Jae-Seok Kim ,  Sang-Min Lee ,  Yun-Ho Jung

发明人： Ji-Ho Kim ,  Jae-Do Roh ,  Jae-Seok Kim ,  Sang-Min Lee ,  Yun-Ho Jung

IPC分类号： H04J1/16

CPC分类号： H04W16/14

摘要： A victim system detector for detecting whether a second wireless communication system uses frequency bands that are used by a first wireless communication system (detecting whether the second wireless communication system is a victim system) includes a correlator and a decision unit. The correlator calculates a correlation value between a frequency domain baseband signal associated with the first wireless communication system and a correlation sequence of the second wireless communication system. The decision unit determines, based on the correlation value, whether the second wireless communication system is a victim system. Therefore, the victim system is detected accurately and efficiently.

摘要翻译： 一种用于检测第二无线通信系统是否使用由第一无线通信系统使用的频带（检测第二无线通信系统是否是受害系统）的受害系统检测器，包括相关器和判定单元。 相关器计算与第一无线通信系统相关联的频域基带信号与第二无线通信系统的相关序列之间的相关值。 决定单元基于相关值来确定第二无线通信系统是否是受害者系统。 因此，准确有效地检测受害者系统。

公开(公告)号：US20070254564A1

公开(公告)日：2007-11-01

申请号：US10580617

申请日：2005-02-16

申请人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

发明人： Eu-Gene Song ,  Ju-Yeol Lee ,  Sung-Min Kim ,  Jae-Seok Kim ,  Hyun-Woo Lee

IPC分类号： B24D11/00

CPC分类号： B24D11/02 ,  B24B37/22

摘要： Disclosed is a base pad of polishing pad, which is used in conjunction with polishing slurry during a chemical-mechanical polishing or planarizing process, and a multilayer pad using the same. Since the base pad according to the present invention does not have fine pores, it is possible to prevent premeation of polishing slurry and water and to avoid nonuniformity of physical properties. Thereby, it is possible to lengthen the lifetime of the polishing pad.

摘要翻译： 公开了一种在化学机械抛光或平面化处理过程中与抛光浆料结合使用的抛光垫的基垫，以及使用其的多层垫。 由于根据本发明的基底垫不具有细孔，因此可以防止研磨浆料和水的前体化，并且避免物理性能的不均匀性。 由此，可以延长抛光垫的寿命。

公开(公告)号：US5727029A

公开(公告)日：1998-03-10

申请号：US575076

申请日：1995-12-19

申请人： In-San Jeon ,  Ik-Su Eo ,  In-Ki Lim ,  Kwang-Il Yeon ,  Jae-Seok Kim

发明人： In-San Jeon ,  Ik-Su Eo ,  In-Ki Lim ,  Kwang-Il Yeon ,  Jae-Seok Kim

IPC分类号： H03M13/00 ,  H03M13/41 ,  H04L1/00 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03M13/3961 ,  H03M13/4107 ,  H04L1/0054

摘要： The present invention relates in general to a channel CODEC to increase the transmitting effect on a communication channel of a communication system, and more specifically to a branch metric module of a viterbi decoder. The module includes an operator for operating and outputting the differential magnitude of two signals, one signal being a code word generated to perform the viterbi decode and the other being a signal transmitted through the channel. An adder sums and outputs the data which is outputted to it from the operator. A receiving code word converter converts the magnitude of any of bits by the linear sampling quantization process, and non-linearly converts it in accordance with a preestimated or predetermined format. A number of operators calculate the magnitude between two signals at the absolute value to convert the magnitude of an inputted generative code word and the magnitude of the non-linear converted receiving code word. The adder sums and outputs the result to a branch metric converter, which converts the output according to the preestimated format.

摘要翻译： 本发明一般涉及增加对通信系统的通信信道的传输效果的信道CODEC，更具体地涉及维特比解码器的分支量度模块。 该模块包括用于操作和输出两个信号的差分幅度的操作器，一个信号是被执行维特比解码而产生的代码字，另一个是通过该信道发送的信号。 加法器对从操作者向其输出的数据进行求和并输出。 接收码字转换器通过线性采样量化处理来转换任何位的幅度，并且根据预先预定的格式非线性地转换它。 许多算子以绝对值计算两个信号之间的幅度，以转换输入的生成码字的大小和非线性转换的接收码字的大小。 加法器将结果相加并输出到分支度量转换器，该转换器根据预先预定的格式转换输出。

公开(公告)号：US08468711B2

公开(公告)日：2013-06-25

申请号：US12934223

申请日：2009-06-02

申请人： Jae-Seok Kim ,  Ju-Han Yoon

发明人： Jae-Seok Kim ,  Ju-Han Yoon

IPC分类号： F26B11/02

CPC分类号： D06F58/22

摘要： Disclosed is a clothes dryer, comprising: a body; a drum rotatably installed at the body; a duct for guiding air exhausted from the drum; and a filter assembly for filtering lint included in the air exhausted from the drum. The filter assembly includes a lint filter and a cover filter, and a lint collector encompassed by the lint filter and the cover filter. The clothes dryer includes sensing means for sensing whether the lint filter has been mounted to a precise position or not. The sensing means consists of a magnet mounted to a mesh frame of the lint filter, and a reed switch mounted to a cover guide.

摘要翻译： 本发明公开了一种干衣机，包括：主体; 可旋转地安装在身体的滚筒; 用于引导从滚筒排出的空气的导管; 以及用于过滤包括在从滚筒排出的空气中的棉绒的过滤器组件。 过滤器组件包括棉绒过滤器和覆盖过滤器，以及由棉绒过滤器和盖过滤器包围的棉绒收集器。 干衣机包括用于检测棉绒过滤器是否已被安装到精确位置的感测装置。 感测装置由安装到棉绒过滤器的网架的磁体和安装到盖导向器的舌簧开关组成。

公开(公告)号：US20110256676A1

公开(公告)日：2011-10-20

申请号：US13048683

申请日：2011-03-15

申请人： Seong-Kyu Yun ,  Jae-Seok Kim

发明人： Seong-Kyu Yun ,  Jae-Seok Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/544 ,  H01L29/7848 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening.

摘要翻译： 制造半导体器件的方法包括在分成至少NMOS形成区域和PMOS形成区域的衬底上形成多晶硅图案和硬掩模图案的集成结构。 在集成结构上形成第一初步绝缘中间层。 执行第一初步绝缘中间层的第一次抛光，直到暴露硬掩模图案的至少一个上表面，以形成第二预绝缘中间层。 蚀刻第二初步绝缘中间层直到硬掩模图案的上表面露出，以形成第三初步绝缘中间层。 执行硬掩模图案和第三预备绝缘中间层的第二次抛光，直到多晶硅图案暴露以形成绝缘中间层。 去除多晶硅图形以形成开口。 金属材料被放弃以在开口中形成栅极电极图案。