公开(公告)号：US07553725B2

公开(公告)日：2009-06-30

申请号：US11488911

申请日：2006-07-18

申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

摘要翻译： 非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。 源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。 非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域 以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。 单元栅极图案和选择线之间的距离小于选择线的宽度。

公开(公告)号：US20070195595A1

公开(公告)日：2007-08-23

申请号：US11600427

申请日：2006-11-16

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Sung-Taeg Kang

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Sung-Taeg Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.

摘要翻译： 非易失性存储器件包括具有一对存储晶体管和一个选择晶体管的存储单元单元。 选择晶体管设置在形成在半导体衬底中的有源区中的一对存储晶体管之间。 提供了两个位线，一个位线连接到该对存储晶体管中对应的一个位线，另一个位线连接到该对存储晶体管中的相应另一个。

公开(公告)号：US07515468B2

公开(公告)日：2009-04-07

申请号：US11600427

申请日：2006-11-16

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Sung-Taeg Kang

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Sung-Taeg Kang

IPC分类号： G11C11/34

CPC分类号： G11C16/0408 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.

摘要翻译： 非易失性存储器件包括具有一对存储晶体管和一个选择晶体管的存储单元单元。 选择晶体管设置在形成在半导体衬底中的有源区中的一对存储晶体管之间。 提供了两个位线，一个位线连接到该对存储晶体管中对应的一个位线，另一个位线连接到该对存储晶体管中的相应另一个。

公开(公告)号：US20080130367A1

公开(公告)日：2008-06-05

申请号：US12027735

申请日：2008-02-07

申请人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

发明人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

IPC分类号： G11C16/14

CPC分类号： G11C7/18 ,  G11C16/16 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

摘要翻译： 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

公开(公告)号：US20070091682A1

公开(公告)日：2007-04-26

申请号：US11427211

申请日：2006-06-28

申请人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

发明人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

摘要翻译： 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

公开(公告)号：US20070045673A1

公开(公告)日：2007-03-01

申请号：US11488911

申请日：2006-07-18

申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

IPC分类号： G11C11/34

CPC分类号： H01L27/11524 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

摘要翻译： 非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。 源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。 非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域 以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。 单元栅极图案和选择线之间的距离小于选择线的宽度。

公开(公告)号：US20060092705A1

公开(公告)日：2006-05-04

申请号：US11256554

申请日：2005-10-21

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5692 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.

摘要翻译： 提供具有多位非易失性存储单元的半导体器件。 半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。 多个晶体管每个包括至少一个控制栅极和至少一个电荷存储区域。 电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。 每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

公开(公告)号：US07521750B2

公开(公告)日：2009-04-21

申请号：US12017239

申请日：2008-01-21

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

IPC分类号： H01L29/76

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5692 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile semiconductor device includes a pair of multi-bit nonvolatile memory unit cells. Each unit cell includes a grid type semiconductor body in which a plurality of parallel semiconductor bodies extend in a first direction and a plurality of parallel semiconductor bodies extend in a second direction perpendicular to the first direction, a channel region formed in a partial region of the semiconductor body along circumferences of the semiconductor bodies that extend in the first direction, a charge storage region formed on the channel region, a plurality of control gates, which are formed on the charge storage region and wherein each of the plurality of control gates is adapted to receive separate control voltages. Each unit cell further includes source and drain regions aligned on both sides of the plurality of control gates and formed in the semiconductor bodies, wherein the pair of unit cells share the source region, and the source region is formed at a cross point of the grid.

摘要翻译： 非易失性半导体器件包括一对多位非易失性存储单元。 每个单电池包括栅格型半导体本体，其中多个平行的半导体本体在第一方向上延伸，并且多个平行的半导体本体在垂直于第一方向的第二方向上延伸，沟道区形成在 半导体本体沿着在第一方向上延伸的半导体本体的周边，形成在沟道区上的电荷存储区域，形成在电荷存储区域上的多个控制栅极，并且其中多个控制栅极中的每一个被适配 以接收单独的控制电压。 每个单元还包括在多个控制栅极的两侧对准并形成在半导体主体中的源极和漏极区域，其中该对单元电池共享源极区域，并且源极区域形成在栅极的交叉点处 。

公开(公告)号：US07339232B2

公开(公告)日：2008-03-04

申请号：US11256554

申请日：2005-10-21

申请人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

发明人： Bo-Young Seo ,  Hee-Seog Jeon ,  Sung-Taeg Kang

IPC分类号： H01L29/76

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5692 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.

摘要翻译： 提供具有多位非易失性存储单元的半导体器件。 半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。 多个晶体管各自包括至少一个控制栅极和至少一个电荷存储区域。 电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。 每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

公开(公告)号：US20080089136A1

公开(公告)日：2008-04-17

申请号：US11870762

申请日：2007-10-11

申请人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

发明人： Hyun-Khe Yoo ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Sung-Gon Choi ,  Bo-Young Seo ,  Chang-Min Jeon ,  Ji-Do Ryu

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

摘要翻译： 非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。 第一感测线和第一字线在基板上彼此平行地相邻地形成。 第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。 耗尽沟道区形成在第一感测线下方的衬底的上部。 在由第一感测线和第一字线露出的衬底的上部形成杂质区。