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18 条记录 (耗时 0.029 秒)

    Nonvolatile memory devices and methods of fabricating the same
    1.
    发明授权
    Nonvolatile memory devices and methods of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US07553725B2

    公开(公告)日：2009-06-30

    申请号：US11488911

    申请日：2006-07-18

    申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11524 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

    摘要翻译： 非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。 源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。 非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域 以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。 单元栅极图案和选择线之间的距离小于选择线的宽度。

    Nonvolatile memory devices and methods of fabricating the same
    2.
    发明申请
    Nonvolatile memory devices and methods of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20070045673A1

    公开(公告)日：2007-03-01

    申请号：US11488911

    申请日：2006-07-18

    申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    IPC分类号： G11C11/34

    CPC分类号： H01L27/11524 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

    摘要翻译： 非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。 源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。 非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域 以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。 单元栅极图案和选择线之间的距离小于选择线的宽度。

    Semiconductor device and methods for forming the same
    8.
    发明授权
    Semiconductor device and methods for forming the same 失效
    半导体装置及其形成方法

    公开(公告)号：US07602004B2

    公开(公告)日：2009-10-13

    申请号：US11585493

    申请日：2006-10-24

    申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Hyok-Ki Kwon

    发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Hyok-Ki Kwon

    IPC分类号： H01L29/788

    CPC分类号： G11C17/12

    摘要： A semiconductor device includes a first transistor and a second transistor formed on a substrate. Each of the first transistor and the second transistor has a first source region, first drain region of a first conductivity type and a gate. The first transistor is an off-transistor and includes a second source/drain region of the first conductivity type which surrounds at least a portion of the first source/drain region in the first transistor.

    摘要翻译： 半导体器件包括形成在衬底上的第一晶体管和第二晶体管。 第一晶体管和第二晶体管中的每一个具有第一源极区域，第一导电类型的第一漏极区域和栅极。 第一晶体管是截止晶体管，并且包括第一导电类型的第二源极/漏极区域，其围绕第一晶体管中的第一源极/漏极区域的至少一部分。

    Nonvolatile memory device and method of fabricating the same
    9.
    发明申请
    Nonvolatile memory device and method of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20070170491A1

    公开(公告)日：2007-07-26

    申请号：US11698658

    申请日：2007-01-26

    申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

    摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

    摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

    Nonvolatile memory device and method of fabricating the same
    10.
    发明授权
    Nonvolatile memory device and method of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US07642593B2

    公开(公告)日：2010-01-05

    申请号：US11698658

    申请日：2007-01-26

    申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

    摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

    摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。