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公开(公告)号：US12236912B2
公开(公告)日：2025-02-25
申请号：US17915712
申请日：2021-10-28
Inventor： Yanping Liao , Yingmeng Miao , Seungmin Lee , Xibin Shao , Shulin Yao , Yinlong Zhang , Qiujie Su , Cong Wang , Dongchuan Chen , Jiantao Liu
IPC: G09G3/36 , G09G3/3266 , G11C19/28
Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.
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公开(公告)号：US12218149B2
公开(公告)日：2025-02-04
申请号：US17637893
申请日：2021-04-27
Inventor： Cong Wang , Yingmeng Miao , Dongchuan Chen , Seungmin Lee , Yanping Liao , Xibin Shao , Jiantao Liu
IPC: G02F1/1362 , G02F1/1333 , G02F1/1339 , G02F1/1343 , G02F1/1368 , H01L27/12
Abstract: A dual gate array substrate includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair; and a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other.
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公开(公告)号：US12159878B2
公开(公告)日：2024-12-03
申请号：US17637485
申请日：2021-03-26
Inventor： Qiujie Su , Zhihua Sun , Tao Yang , Dongchuan Chen , Yingmeng Miao , Jiantao Liu , Seungmin Lee
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L27/12
Abstract: The present disclosure relates to an array substrate and a display device. The array substrate may include: a first substrate, and a plurality of pixel groups and a plurality of columns of data lines formed on the first substrate; wherein the plurality of pixel groups are arranged in an array along a row direction and a column direction, and each pixel group includes two sub-pixels arranged in the row direction; at least one sub-pixel of one of any two adjacent pixel groups in the row direction corresponds to the same color as one sub-pixel of the other pixel group; and any two adjacent sub-pixels in the row direction correspond to different colors; and each column of data line and each column of pixel groups are alternately arranged in the row direction.
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公开(公告)号：US12107073B2
公开(公告)日：2024-10-01
申请号：US17429929
申请日：2020-10-27
Inventor： Zhihua Sun , Yanping Liao , Seungmin Lee , Qiujie Su , Feng Qu , Yingmeng Miao , Xibin Shao
IPC: H01L25/065 , H01L25/00 , H01L23/12
CPC classification number: H01L25/0655 , H01L25/50 , H01L23/12
Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.
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公开(公告)号：US12039907B2
公开(公告)日：2024-07-16
申请号：US18457637
申请日：2023-08-29
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1≤k≤K≤N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n−i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1
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Patent Agency Ranking
公开(公告)号：US10059879B2
公开(公告)日：2018-08-28
申请号：US14894798
申请日：2015-06-18
Inventor： Feifei Wang , Xibin Shao , Dan Wang , Seungmin Lee , Honglin Zhang , Hebin Zhao , Ting Dong , Yingying Qu
IPC: C09K19/38 , G02F1/1335 , C09K19/58 , G02B5/30 , C09K19/54 , G02F1/1333 , G02F1/1341 , C09K19/20 , C09K19/04 , C09K19/32
CPC classification number: C09K19/3814 , C09K19/2007 , C09K19/3809 , C09K19/3852 , C09K19/54 , C09K19/586 , C09K2019/0448 , C09K2019/2042 , C09K2019/2078 , C09K2019/323 , C09K2219/03 , G02B5/3016 , G02B5/3083 , G02F1/133382 , G02F1/1335 , G02F1/13363 , G02F1/1341 , G02F2001/133631
Abstract: A liquid crystal composition comprises a photo-polymerizable liquid crystal mixture and a heat-polymerizable liquid crystal mixture, and the two mixtures have opposite rotatory directions. A patterned phase delay film is prepared from the liquid crystal composition. A display device comprises the phase delay film. The preparation of the patterned phase-delay film can be implemented by a two-step polymerization process including UV-polymerization and heat-polymerization. The process is simple and the costs are low.
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公开(公告)号：US11899321B2
公开(公告)日：2024-02-13
申请号：US17422461
申请日：2020-02-26
Inventor： Liangliang Jiang , Heng Li , Lei Guo , Ke Dai , Yanping Liao , Seungmin Lee
IPC: G02F1/1362
CPC classification number: G02F1/136209 , G02F1/136286
Abstract: The present disclosure provides a liquid crystal display panel and a liquid crystal display device. The liquid crystal display panel includes a plurality of sub-pixels defined by a light shielding matrix, and an array substrate and an opposing substrate arranged to be spaced apart from each other. The opposing substrate includes a first substrate and a plurality of spacers, wherein the spacers are on a side of the first substrate close to the array substrate and being within a light shielding area of the light shielding matrix. The array substrate includes a second substrate and a plurality of protrusion structures, wherein the protrusion structures are on a side of the second substrate close to the opposing substrate, and being within the light shielding area of the light shielding matrix.
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公开(公告)号：US11783744B2
公开(公告)日：2023-10-10
申请号：US17445810
申请日：2021-08-24
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1≤k≤K≤N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n−i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1
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公开(公告)号：US20230196961A1
公开(公告)日：2023-06-22
申请号：US18082691
申请日：2022-12-16
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yangping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0267 , G09G2300/0408 , G09G2310/08 , G09G2300/08 , G09G2310/0243 , G09G2310/0286
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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公开(公告)号：US11442303B2
公开(公告)日：2022-09-13
申请号：US16959286
申请日：2019-08-20
Inventor： Yifu Chen , Seungmin Lee , Yanping Liao , Lei Guo , Yingying Qu , Zhe Li , Liangliang Jiang , Lifeng Lin , Lan Xin , Zhihua Sun
IPC: G02F1/1333 , G02F1/1335 , G02F1/13357 , G02F1/1339
Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a first substrate; at least one underlaying structure, arranged on the first substrate and in a non-display region of at least one side of a display region of the display panel; and at least one supporting structure, arranged on one side, facing away from the first substrate, of the at least one underlaying structure, where an orthographic projection of the supporting structure on the first substrate is within a range of an orthographic projection of the underlaying structure on the first substrate.
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