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    On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode
    2.
    发明授权
    On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode 有权
    片内擦除脉冲计数器，用于高效擦除验证BIST（内置自检）模式

    公开(公告)号：US06665214B1

    公开(公告)日：2003-12-16

    申请号：US10200330

    申请日：2002-07-22

    申请人： Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Weng Fook Lee ,  Boon Tang Teh

    发明人： Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Weng Fook Lee ,  Boon Tang Teh

    IPC分类号： G11C1606

    CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/02 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5002

    摘要： In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.

    摘要翻译： 在用于监视施加在制造在半导体衬底上的快闪存储器单元的扇区上的擦除脉冲的方法和系统中，在半导体衬底上制造脉冲计数器和脉冲计数器控制器。 脉冲计数器控制器输入最大数量，并且如果在擦除验证期间扇区的闪速存储单元不通过小于刷新扇区上最大擦除脉冲数的擦除验证，则输出扇区失败的指示BIST（Built- 自检）模式。 在一个示例中，最大数量是需要施加在扇区上的擦除脉冲的对角线总数的百分比，直到扇区的对角线位置处的每个闪存单元通过擦除验证。

    Method and system for embedded chip erase verification
    4.
    发明授权
    Method and system for embedded chip erase verification 有权
    嵌入式芯片擦除验证方法和系统

    公开(公告)号：US06331951B1

    公开(公告)日：2001-12-18

    申请号：US09717550

    申请日：2000-11-21

    申请人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

    发明人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

    IPC分类号： G11C1606

    CPC分类号： G11C16/344 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3445

    摘要： A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.

    摘要翻译： 公开了用于验证存储器单元擦除的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括选择性地验证小区的第一比特和小区的第二比特之一的适当擦除，如果小区的第一和第二比特被正确擦除，则确定双比特存储单元被适当地擦除，并且选择性地擦除 如果第一和第二位之一没有被正确擦除，则单元的第一和第二位中的至少一个位。 该方法还可以包括在选择性地擦除第一和第二比特中的至少一个之后，选择性地重新验证第一和第二比特之一的适当擦除。

    Method and apparatus for soft program verification in a memory device
    5.
    发明授权
    Method and apparatus for soft program verification in a memory device 有权
    用于在存储器件中进行软程序验证的方法和装置

    公开(公告)号：US06532175B1

    公开(公告)日：2003-03-11

    申请号：US10050650

    申请日：2002-01-16

    申请人： Santosh K. Yachareni ,  Edward V. Bautista, Jr. ,  Weng Fook Lee

    发明人： Santosh K. Yachareni ,  Edward V. Bautista, Jr. ,  Weng Fook Lee

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3459

    摘要： Methods and apparatus are disclosed for verifying soft programming of one or more memory cells in a memory device. The methods comprise providing a voltage source to the core cell gate, and verifying soft programming of the cell after overshoot in the regulated voltage source has settled. Also disclosed are memory devices having a logic circuit providing a regulated voltage source to the cell gate during a soft program verify operation, and a sensor to verify soft programming of the cell when a first voltage is applied to the gate from the regulated voltage source. The logic circuit provides a soft program verify signal to the sensor to verify soft programming after overshoot in the voltage source has settled.

    摘要翻译： 公开了用于验证存储器件中的一个或多个存储器单元的软编程的方法和装置。 所述方法包括向核心单元栅极提供电压源，以及在调节电压源中的过冲后确认电池的软编程。 还公开了存储器件，其具有在软程序验证操作期间向单元栅极提供调节电压源的逻辑电路，以及当从调节电压源向栅极施加第一电压时验证该单元的软编程的传感器。 逻辑电路向传感器提供软程序验证信号，以验证电压源过冲后的软编程。

    System and method to facilitate stabilization of reference voltage signals in memory devices
    8.
    发明授权
    System and method to facilitate stabilization of reference voltage signals in memory devices 有权
    有助于稳定存储器件中参考电压信号的系统和方法

    公开(公告)号：US06459628B1

    公开(公告)日：2002-10-01

    申请号：US09824166

    申请日：2001-04-02

    申请人： Edward V. Bautista, Jr. ,  Weng Fook Lee ,  Santosh K. Yachareni

    发明人： Edward V. Bautista, Jr. ,  Weng Fook Lee ,  Santosh K. Yachareni

    IPC分类号： G11C700

    CPC分类号： G11C16/32 ,  G11C16/30

    摘要： A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.

    摘要翻译： 用于存储器装置的等待系统可操作以提供等待信号以相对于存储器单元延迟每个操作的性能。 在给定用户模式期间，等待信号首先延迟相对于存储器单元的至少一个初始操作的性能第一持续时间。 在初始等待信号之后，提供后续的等待信号以在给定的用户模式期间相对于存储器单元的后续操作的性能延迟小于第一持续时间的第二持续时间。

    System and method for erase voltage control during multiple sector erase of a flash memory device
    9.
    发明授权
    System and method for erase voltage control during multiple sector erase of a flash memory device 有权
    闪存器件的多扇区擦除期间擦除电压控制的系统和方法

    公开(公告)号：US06891752B1

    公开(公告)日：2005-05-10

    申请号：US10210378

    申请日：2002-07-31

    申请人： Edward V. Bautista ,  Ken Cheong Cheah ,  Weng Fook Lee

    发明人： Edward V. Bautista ,  Ken Cheong Cheah ,  Weng Fook Lee

    IPC分类号： G11C16/16 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3472 ,  G11C16/16 ,  G11C16/344

    摘要： A method for erasing a flash memory. In a flash memory device having multiple sectors a plurality of sectors is selected for erase (810). a subset of sectors is selected (815) and an erase pulse is applied simultaneously to all sectors in the subset (820). After the application of an erase pulse having an initial voltage value, at least one sector of the subset is verified (825). If there is at least one unerased cell in the verified sector, the erase voltage is adjusted (830) and another erase pulse is applied to the subset of sectors (820). The adjustment of the erase voltage may be a function of the number of times that an erase pulse has been applied to the subset. This cycle is repeated on the subset until the selected sector is verified as erased. After a sector is verified, the erase/verify cycle is applied to one or more of the remaining sectors in the subset until each of the remaining sectors has been verified as erased. After all of the sectors in the subset are erased, the erase voltage is reset to its initial value (840) and another subset of sectors is selected for erase/verify as described above (815). The process may be repeated until all of the memory sectors in the device have been erased (850). A flash memory device with embedded logic may be used to execute the method.

    摘要翻译： 一种擦除闪存的方法。 在具有多个扇区的快闪存储器件中，选择多个扇区用于擦除（810）。 选择扇区的子集（815），并且将消除脉冲同时应用于子集（820）中的所有扇区。 在施加具有初始电压值的擦除脉冲之后，验证该子集的至少一个扇区（825）。 如果在验证扇区中存在至少一个未故障单元，则调整擦除电压（830），并向扇区子集（820）施加另一擦除脉冲。 擦除电压的调整可以是将擦除脉冲施加到子集的次数的函数。 在子集上重复该循环，直到所选择的扇区被确认为擦除。 在验证扇区之后，将擦除/验证周期应用于子集中的一个或多个剩余扇区，直到其余扇区中的每一个已被验证为已擦除。 在子集中的所有扇区被擦除之后，擦除电压被复位到其初始值（840），并且如上所述（815）选择另一扇区子集进行擦除/验证。 可以重复该过程，直到设备中的所有存储器扇区被擦除（850）。 具有嵌入式逻辑的闪速存储器件可用于执行该方法。

    Method and apparatus for pre-charging negative pump MOS regulation capacitors
    10.
    发明授权
    Method and apparatus for pre-charging negative pump MOS regulation capacitors 失效
    负电泵MOS调节电容器预充电方法和装置

    公开(公告)号：US07057949B1

    公开(公告)日：2006-06-06

    申请号：US10050342

    申请日：2002-01-16

    申请人： Feng Pan ,  Weng Fook Lee ,  Edward V. Bautista, Jr. ,  Santosh K. Yachareni

    发明人： Feng Pan ,  Weng Fook Lee ,  Edward V. Bautista, Jr. ,  Santosh K. Yachareni

    IPC分类号： G11C7/00

    CPC分类号： G11C5/145 ,  G11C16/30

    摘要： Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.

    摘要翻译： 公开了用于在半导体存储器件中使用负栅极电压擦除核心存储器单元的方法和装置，其中在核心单元擦除操作期间，根据预充电信号对负泵MOS调节电容器进行预充电。 然后使用预充电的负泵MOS调节电容器调节负电压泵，以提供负栅极电压。 公开了一种用于在存储器件中的核心单元擦除操作期间对负泵MOS调节电容器预充电的装置，其包括连接在参考电压和负泵MOS调节电容器之间的开关，以及提供预充电的预充电控制电路 充电信号到开关，以选择性地将参考电压连接到负泵MOS调节电容器，以在擦除操作中对其进行预充电。