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10 条记录 (耗时 0.037 秒)

    Method and apparatus for ensuring backward compatibility in a bucket rendering system
    5.
    发明授权
    Method and apparatus for ensuring backward compatibility in a bucket rendering system 有权
    用于确保铲斗再现系统中的向后兼容性的方法和装置

    公开(公告)号：US06466217B1

    公开(公告)日：2002-10-15

    申请号：US09470924

    申请日：1999-12-22

    申请人： Hsien-cheng Emile Hsieh ,  Vladimir M. Pentkovski

    发明人： Hsien-cheng Emile Hsieh ,  Vladimir M. Pentkovski

    IPC分类号： G06F120

    CPC分类号： G06T15/005

    摘要： A method and apparatus of rendering an image is disclosed. In one embodiment, a graphic system has a switch detector, which detects a switch condition in the graphics system. The graphics system also has a rendering block, which renders a plurality of layers according to the detected switch condition.

    摘要翻译： 公开了渲染图像的方法和装置。在一个实施例中，图形系统具有开关检测器，其检测图形系统中的开关状态。 图形系统还具有渲染块，其根据检测到的切换条件呈现多个层。

    Streaming processing of biological sequence matching
    6.
    发明授权
    Streaming processing of biological sequence matching 失效
    生物序列匹配的流处理

    公开(公告)号：US07512498B2

    公开(公告)日：2009-03-31

    申请号：US10331334

    申请日：2002-12-31

    申请人： Vladimir M. Pentkovski

    发明人： Vladimir M. Pentkovski

    IPC分类号： G01N33/48

    CPC分类号： G06F17/30985 ,  G06F19/22 ,  G06F19/28 ,  Y10S707/99936

    摘要： A data system is provided for biological sequence matching. The system includes a system memory, a cache controller coupled to the system memory, a first cache coupled to the cache controller to receive non-temporal data from the system memory, and a second cache coupled to the cache controller to receive temporal data from the system memory. The first cache to also receive the temporal data from the second cache. The system further includes a processor coupled to the cache controller and the first cache.

    摘要翻译： 提供了用于生物序列匹配的数据系统。 该系统包括系统存储器，耦合到系统存储器的高速缓存控制器，耦合到高速缓存控制器以从系统存储器接收非时间数据的第一高速缓存器，以及耦合到高速缓存控制器的第二高速缓存器，用于从 系统内存 第一缓存也从第二缓存接收时间数据。 系统还包括耦合到高速缓存控制器和第一高速缓存的处理器。

    Method and apparatus for processing 2D operations in a tiled graphics architecture
    7.
    发明授权
    Method and apparatus for processing 2D operations in a tiled graphics architecture 有权
    在平铺图形架构中处理2D操作的方法和装置

    公开(公告)号：US06819321B1

    公开(公告)日：2004-11-16

    申请号：US09540615

    申请日：2000-03-31

    申请人： Hsien-Cheng Hsieh ,  Vladimir M. Pentkovski ,  Hsin-Chu Tsai

    发明人： Hsien-Cheng Hsieh ,  Vladimir M. Pentkovski ,  Hsin-Chu Tsai

    IPC分类号： G06F120

    CPC分类号： G06T11/40 ,  G06T15/005

    摘要： A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

    摘要翻译： 公开了一种在平铺图形架构中处理2D操作的方法。 图形控制器处理3D原始图像和2D图形操作。 使用众所周知的技术将3D原语分类到存储盒中。 当2D处理操作被处理时，2D blit操作也被分类成bin。 然后将排序的3D原语和排序的2D blit操作以逐位方式传送给blit和呈现引擎。 通过将2D blit操作与3D原语一起排列成bin，无论何时2D blit操作需要处理，都不需要将bin（发送原语发送到渲染引擎）。 将2D打印操作分类到存储空间可以降低图形缓存未命中的频率，并提高图形内存带宽利用率，从而提高计算机系统的整体性能。

    System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
    9.
    发明授权
    System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data 失效
    用于写入具有单个指令的非连续字节的系统，其具有与对应于打包数据的各个块的识别字节掩码的操作数

    公开(公告)号：US06173393B2

    公开(公告)日：2001-01-09

    申请号：US09052802

    申请日：1998-03-31

    申请人： Salvador Palanca ,  Vladimir M. Pentkovski ,  Suresh N. Kuttuva ,  Praveen B. Mosur

    发明人： Salvador Palanca ,  Vladimir M. Pentkovski ,  Suresh N. Kuttuva ,  Praveen B. Mosur

    IPC分类号： G06F1500

    CPC分类号： G06F9/30032 ,  G06F9/30036

    摘要： A processor comprising a decoder, an execution core and a bus controller. The decoder is operative to decode instructions received by the processor including a move instruction comprising a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks. The execution core, coupled to the decoder, is operative to receive the decoded move instruction and analyze each individual byte mask of the plurality of byte masks to identify corresponding bytes within the plurality of bytes of packed data that are write-enabled. The bus controller, coupled to the execution core, is operative to write select bytes of the plurality of bytes of packed data to an implicitly defined location based, at least in part, on the write enabled byte masks identified by the execution core.

    摘要翻译： 一种包括解码器，执行核心和总线控制器的处理器。 解码器用于解码由处理器接收的指令，包括移动指令，该移动指令包括标识多个字节的压缩数据的第一操作数和标识对应的多个字节掩码的第二操作数。 耦合到解码器的执行核心可操作以接收解码的移动指令并且分析多个字节掩码的每个单独的字节掩码以识别被写入使能的打包数据的多个字节内的相应字节。 耦合到执行核心的总线控制器可操作地至少部分地基于由执行核心识别的可写使能字节掩码，将多个打包数据的多个字节的选择字节写入隐式定义的位置。