公开(公告)号：US5706492A

公开(公告)日：1998-01-06

申请号：US687975

申请日：1996-07-29

申请人： Bradley D. Hoyt ,  Glenn I. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn I. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

公开(公告)号：US5944817A

公开(公告)日：1999-08-31

申请号：US168305

申请日：1998-10-07

申请人： Bradley D. Hoyt ,  Glenn I. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn I. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

摘要翻译： 公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。 分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。 存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。 当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。 基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。 当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

公开(公告)号：US5812839A

公开(公告)日：1998-09-22

申请号：US851141

申请日：1997-05-05

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3844 ,  G06F9/3863 ,  G06F9/3885

摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.

摘要翻译： 公开了一种用于流水线处理器的四级分支指令解析系统。 分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。 第二阶段解码所有提取的指令。 如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。 解码阶段验证分支预测阶段所做的所有分支预测。 最后，解码阶段对分支预测阶段未预测的分支进行分支预测。 第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。 分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。 最终的分支解决阶段退出所有分支指令。 退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

公开(公告)号：US5768576A

公开(公告)日：1998-06-16

申请号：US739743

申请日：1996-10-29

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4426

摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.

摘要翻译： 公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。 该方法和设备分四个阶段解析子程序指令。 第一阶段预测指令流中的调用子程序指令和子程序返回指令。 当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。 第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。 第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。 每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。 相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。 第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。 第三阶段执行从子程序返回指令，使得预测得到验证。 最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

公开(公告)号：US5903751A

公开(公告)日：1999-05-11

申请号：US931807

申请日：1997-09-16

申请人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

发明人： Bradley D. Hoyt ,  Glenn J. Hinton ,  David B. Papworth ,  Ashwani Kumar Gupta ,  Michael Alan Fetterman ,  Subramanian Natarajan ,  Sunil Shenoy ,  Reynold V. D'Sa

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

摘要翻译： 公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。 分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。 存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。 当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。 基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。 当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

公开(公告)号：US5845100A

公开(公告)日：1998-12-01

申请号：US806022

申请日：1997-02-24

申请人： Ashwani Kumar Gupta ,  Glenn J. Hinton ,  Chan W. Lee

发明人： Ashwani Kumar Gupta ,  Glenn J. Hinton ,  Chan W. Lee

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30152 ,  G06F9/3816

摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

摘要翻译： 一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。 指令代码块通过缓冲器输入获取和输入。 第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。 指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路​​复用器。 指令缓冲多路​​复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。 旋转器接收指示初始字节的输入指针。 旋转器将从初始字节开始的指令代码块输出到指令解码器。

公开(公告)号：US5758116A

公开(公告)日：1998-05-26

申请号：US316208

申请日：1994-09-30

申请人： Chan W. Lee ,  Gary L. Brown ,  Adrian L. Carbine ,  Ashwani Kumar Gupta

发明人： Chan W. Lee ,  Gary L. Brown ,  Adrian L. Carbine ,  Ashwani Kumar Gupta

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/04

CPC分类号： G06F9/30152 ,  G06F9/3816 ,  G06F9/382

摘要： A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instruction, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started. The slow carry chain circuitry processes information from a subset of the input buffer at a time, and thus requires more than one iteration, with a different set of PLA inputs provided by a multiplexer upon each iteration. A SCC latch latches the output length marks from the slow carry chain circuitry and provides an output to the instruction decoder.

摘要翻译： 一种用于将指示指令代码块中的指令的第一字节和最后字节的输出长度标记提供给指令解码器的电路和方法。 指令代码块被输入到输入缓冲器。 多个可编程逻辑阵列（PLAs）被耦合以从输入缓冲器接收预定的字节集合并在输出端提供指令信息。 PLA的输出耦合到快速进位链电路，其快速处理来自PLAs的信息，并且在每次发现指令的第一个字节时提供START标记，并且在每次发现指令的最后一个字节时提供END标记 。 长度信息被提供给跨越到指令代码的下一个输入缓冲器的长度计算的环绕逻辑。 FCC锁存器锁存来自快速进位链电路的输出长度标记，并向指令解码器提供输出。 如果长度变化的前缀和匹配的长度变化的操作码都存在于指令中，则快速进位链电路中的处理被中止，并且慢进位链电路中的处理开始。 慢进位链电路一次处理来自输入缓冲器的子集的信息，因此需要多于一次的迭代，在每次迭代时由多路复用器提供的不同的PLA输入集合。 SCC锁存器从慢进位链电路锁存输出长度标记，并向指令解码器提供输出。

公开(公告)号：US5694589A

公开(公告)日：1997-12-02

申请号：US490068

申请日：1995-06-13

申请人： Andrew F. Glew ,  Ashwani Kumar Gupta

发明人： Andrew F. Glew ,  Ashwani Kumar Gupta

IPC分类号： G06F9/30 ,  G06F11/36 ,  G06F9/44

CPC分类号： G06F11/3648 ,  G06F9/30152 ,  G06F9/382

摘要： Code breakpoint detection logic for a superscalar microprocessor. Superscalar operation in a microprocessor is maintained with a single breakpoint detection mechanism which performs breakpoint detection prior to instruction decoding. One bit for each byte in an instruction packet is provided as a result of a comparison of the aligned instruction fetch to the debug registers. After decoding, if the first byte of an instruction has an appended breakpoint true bit, then an event is signaled for breakpoint handling by the superscalar microprocessor.

摘要翻译： 用于超标量微处理器的代码断点检测逻辑。 使用在指令解码之前执行断点检测的单个断点检测机构来维持微处理器中的超标量操作。 作为对齐指令提取与调试寄存器进行比较的结果，提供指令包中每个字节的一位。 在解码之后，如果指令的第一个字节具有附加的断点真位，则用超标量微处理器发送事件以进行断点处理。